Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Patent
1992-07-28
1995-04-04
Oberley, Alvin E.
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
345204, 326 98, 326113, G09G 336
Patent
active
054041511
ABSTRACT:
A scanning circuit according to the invention has a form of integrated thin film transistors on a substrate, comprising a multiplicity of serially interconnected stages of pass transistors or clocked inverters for successive transmission of a signal with a predetermined delay. Each stage includes only one pass transistor or clocked inverter which is operated by a pair of mutually inverted clock puls. Each stage also comprises an output buffer circuit for providing a scanning signal having a frequency twice as large as said clock pulses by receiving the output of the corresponding pass transistor or clocked inverter via an NOR gate which is operated by one of tile paired clock pulses. The scanning circuit is thus capable of doubly fast scanning of a display, e.g. a high resolution display. The scanning circuit is simple in structure, so that it occupies only a small area on a substrate and gives high yield and reliability.
REFERENCES:
patent: 4785297 (1988-11-01), Sekiya
patent: 5194853 (1993-03-01), Asada
NEC Corporation
Oberley Alvin E.
Oh Minsun
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