Scanning circuit

Details Scanning circuit Scanning circuit

1991-12-19

1993-03-16

Westin, Edward P.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340719, 340789, 307481, G09G 318, H03K 19096

Patent

active

051948532

ABSTRACT:
A scanning circuit for successively scanning a plural number of capacitive loads comprising: a delay circuit 101 for delaying a supplied pulse signal from a previous stage in accordance with a first clock signal; a switching transistor 102 which is controlled by the first clock signal; an EXNOR circuit 103 which judges whether or not the signal generated by the delay circuit 101 is correct; a non-inverting buffer circuit 104 for reserve of the delay circuit 101; switching transistors 105 and 106 which are controlled in accordance with the signal generated by the EXNOR circuit 103; and an output buffer circuit 107 which is controlled in accordance with the first clock signal or a second clock signal. Accordingly, the scanning circuit can operate correctly even if one of the delay circuit 101 or the non-inverting buffer circuit 104 fails.

REFERENCES:
patent: 4710648 (1987-12-01), Hanamura et al.
patent: 4789899 (1988-12-01), Takahashi et al.
patent: 5021774 (1991-06-01), Ohwada et al.
patent: 5063378 (1991-11-01), Roach

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