Scanning capacitance sample preparation technique

Details Scanning capacitance sample preparation technique Scanning capacitance sample preparation technique

1999-11-30

2003-07-29

Pham, Long (Department: 2823)

Fishing, trapping, and vermin destroying

C438S014000, C438S018000

Reexamination Certificate

active

06599132

ABSTRACT:

FIELD OF THE INVENTION
The field of the present invention relates generally to a technique for cross-sectioning a crystalline material to provide a substantially atomically smooth surface. In particular, the field of the invention relates to preparation of semiconductor samples for Scanning Capacitance Microscopy (SCM), Scanning Tunneling Microscopy (STM) or other analysis techniques.
BACKGROUND
Many material analysis techniques require a sample to be cross-sectioned; that is, to be sliced in a direction substantially different than the planar surface. The semiconductor industry typically builds devices in a planar fashion, using thin-film techniques. As semiconductor devices shrink to sub-micron, and beyond sub 0.1 micron critical planar dimensions, analysis techniques for two-dimensional, cross-sectional images have become inadequate.
Much of the economic success of the semiconductor industry depends on the continued shrinking of devices, which makes circuits faster and more compact, while lowering the cost. Microprocessor and DRAM device dimensions have shrunk from critical dimensions of approximately 0.8 microns in 1990 to 0.18 microns in 1999.
It is currently possible to build devices for which there is no conventional way to obtain substantially accurate images of two dimensional dopant profiles. This impediment increases the difficulty in designing the next generation of smaller devices, since process or device improvements rely on knowledge of device geometries and electrical carrier distributions. Device design is typically an iterative process, where a prototype device is built, then tested and studied, and then the design is improved based on the knowledge gained from the first prototype. This design loop can occur several times before a production design is finished.
Additionally, Computer Aided Design (CAD) tools specific to the semiconductor industry rely on physical model development and calibration for predictive modeling of device designs before the actual devices are built. Therefore, part of the design loop involves CAD modeling, and those CAD models rely on accurate measurement of test devices.
A semiconductor electronic device operates by controlling the position and motion of charge carriers, typically electrons and holes. Dopants are introduced into a crystalline semiconductor material to locally supply carriers and to affect their behavior when the device is electrically operated. The designer of such devices must be able to create a process to place the dopants with spatial accuracy to optimize the device performance. As devices are shrunk to improve performance, dopant placement accuracy is vital to obtaining working devices and acceptable manufacturing yields.
Techniques for dopant profiling have been largely limited by two-dimensional spatial resolution. One dimensional techniques, such as Secondary Ion Mass Spectrometry (SIMS) have high spatial resolution in the depth dimension, but require areal dimensions larger than most semiconductor devices of interest. Cleave-and-Stain techniques provide two-dimensional images, but spatial resolution is far from adequate for modern device dimensions, and quantization of dopant concentration is severely limited. Conventional spreading resistance techniques are also limited in spatial resolution to dimensions much larger than most devices of interest today. Higher spatial resolution is needed for two dimensional, cross-sectional analysis techniques.
Scanning Capacitance Microscopy (SCM) is a fairly recent development for high spatial resolution images of electrical charge concentrations, which can represent the electrically active dopant concentration in the 1×10
15
to 5×10
21
per cubic cm range. Scanning Capacitance Microscopy apparatus is explained in U.S. Pat No. 5,065,103, which is incorporated herein by reference. This measurement technique uses an Atomic Force Microscope (AFM) apparatus, combined with a high-frequency capacitance sensor to extract local capacitance versus electrical potential (dC/dV) information. By scanning the AFM/SCM tip in two dimensions and processing dC/dV information, a spatial image of electrical charge concentrations is obtained. This technique can image the charge concentrations in two dimensions across the surface of a sample. No information of charge concentrations in the depth dimension is obtained with this method.
Sample Preparation
Researchers at Texas Instruments, University of Texas, Intel, University of Utah, Digital Instruments, The National Institute of Standards and others have used standard techniques for cleaving, and mechanically polishing the cleaved surface for two-dimensional imaging with one dimension being substantially orthogonal to the sample surface. H. Edwards, et. al., “Scanning Capacitance Spectroscopy: An analytical technique for pn-junction delineation in Si devices,”
Appl. Phys. Lett
., 72, 698 (1998) and A. Erickson, et. al., “Quantitative Scanning Capacitance Microscopy analysis of Two-Dimensional dopant concentrations at nanoscale dimensions,”
J Elec. Mat
., 25, 301 (1996), U.S. Pat. No. 5,710,052, and U.S. Pat. No. 5,520,769 are incorporated herein by reference. The technique depends on conventional methods normally employed for Transmission Electron Microscopy (TEM) or Scanning Electron Microscopy (SEM) sample preparation. Mechanical polishing produces an undesirable atomically rough surface, which adds noise and degrades spatial resolution and quantization of charge. The cleaving process is very imprecise, therefore making the selection of a specific device for analysis difficult or impossible. Also, cleaving a wafer is destructive at the wafer level, severely restricting further processing of that wafer. Therefore, this technique is not practical as an in-situ process monitor since an entire wafer must be broken in order to analyze one process step.
Another example of a conventional attempt to solve the problem is a technique used by Charles Evans and Associates. K. J. Chao, et. al., “
Applications of AFM and SCM in Semiconductor Devices
,” Charles Evans and Associates Analytical Measurement Conference, Sunnyvale, Calif. 1999, incorporated herein by reference. They have developed a technique wherein a device is selected by photolithography. Plasma etching is then used to form an orthogonal surface which cross-sections the device of interest. The resulting structure resembles a pillar or thin vertical wall. The pillar or wall on which the cross-section exists is toppled so as to provide direct topside access to the orthogonal, cross-sectional surface. Mechanical polishing can be used on this newly formed surface if the toppled structure is mechanically secured to the wafer or another substrate. SCM is then used to image the charges in the cross-section of a device. A major disadvantage of this technique is that the cross-sectional surface is atomically rough since it was formed with plasma etching and possibly a subsequent mechanical polish. This has the undesirable effect of adding noise, degrading spatial resolution and quantization of charges. Another disadvantage of this approach is that each pillar containing a selected device for analysis must be manually toppled and secured to a substrate. Furthermore, an electrical ground must be provided for the small, toppled piece. Such intricate handling of small parts may introduce contamination and measurement errors, and requires additional preparation time by a skilled, dexterous person.
What is needed is a sample preparation technique to produce a substantially atomically smooth surface at an angle to the original sample surface, without breaking the entire wafer. It is also desirable to specifically select one or more devices for analysis, while leaving other devices on the wafer undisturbed. Furthermore, it would be desirable to select a specific portion of or exact location on specific devices. It would be advantageous to eliminate the handling or anchoring of small parts, and to be able to prepare many devices on a substrate for analysis at once, without operating on each d

Affiliated with

Also associated with

Rating

Scanning capacitance sample preparation technique does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scanning capacitance sample preparation technique, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scanning capacitance sample preparation technique will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3008188