Scannable system with addressable scan reset groups

Details Scannable system with addressable scan reset groups Scannable system with addressable scan reset groups

1991-03-15

1993-12-14

Baker, Stephen M.

Excavating

3072723, G01R 31318

Patent

active

052710190

ABSTRACT:
A set of scan latches is partitioned into unique groups where each group is addressable by a group initializing circuit. The group initializing circuit initializes all the latches of an addressed group to a predefined state thereby quickly loading a test vector into the addressed group of scan latches while leaving other latches undisturbed.

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Author unknown, "Shift Register Latch for Delay Testing", IBM Tech. Discl. Bull., vol. 32, No. 4A, Sep. 1989, pp. 231-232.

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