Scannable synchronizer having a deceased resolving time

Details Scannable synchronizer having a deceased resolving time Scannable synchronizer having a deceased resolving time

2005-05-17

2005-05-17

Burd, Kevin M (Department: 2631)

Pulse or digital communications

Synchronizers

C327S202000

Reexamination Certificate

active

06895061

ABSTRACT:
The present invention provides a synchronizer for receiving an incoming data signal of a first clock domain and for outputting a data signal of a second clock domain. The synchronizer comprises an input stage, a master latch, a transfer stage and a slave latch. The input stage receives the data signal of the first clock domain and outputs the data signal to the master latch when the input stage is clocked with a master clock signal. The master latch stores the data signal at a storage node of the master latch. The master latch has a resolve time associated with it during which the master latch seeks to resolve the data signal to a logic 0 or a logic 1. The transfer stage transfers the data signal stored in the master latch to the slave latch when the transfer stage is clocked with a slave clock signal.

REFERENCES:
patent: 5548620 (1996-08-01), Rogers
patent: 5576651 (1996-11-01), Phillips
patent: 5793227 (1998-08-01), Goldrian

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