Data processing: structural design – modeling – simulation – and em – Structural design
Reexamination Certificate
1998-07-16
2001-09-11
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Structural design
C703S004000, C714S726000, C714S727000, C714S728000
Reexamination Certificate
active
06289295
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to transistor circuit configurations, and are more particularly directed to scannable circuits, systems, and methods implementing transistors having differing threshold voltages.
In many modem circuit designs, it is desirable to increase the speed of operation of the circuit application. This is commonly true in circuits such as a microprocessor, an application specific integrated circuit (“ASIC”), and a digital signal processor (“DSP”). In such types of circuits, during design the circuits which make up speed-limiting portions or affect the speed of the circuit are constantly scrutinized and re-designed to increase the overall circuit speed. Increased speed increases performance and, therefore, permits more detailed and sophisticated processing capabilities in a shorter amount of time.
Another consideration in the design of modem circuit applications involves testing circuit devices once they are constructed. Typically, such testing is a one time occurrence at the beginning of the life cycle of the device, and provided the device successfully meets the testing criteria, it is then shipped for eventual use in some application. In the context of scannable circuits, this testing is achieved by including within the device some type of scan data path which may be selected as an alternative to the true data path for the device. For example, a multiplexer type input may be used whereby selection of a first path through the multiplexer provides scan data to the circuit device whereas selection of a second path through the multiplexer provides normal operational data to the circuit device. Given this capability, scan data may be input to the device for testing purposes, and then an output or other operational manifestations may be recorded and/or observed to ensure that the circuit device is properly operating.
The present inventor has recognized that the two design considerations set forth above, while important and often critical, also may counteract one another in certain respects. More particularly, while increasing the speed of circuit operation is a key design consideration, the inclusion of additional circuitry necessary to accomplish scannability may limit the speed of circuit operation. Indeed, the scope and design of the scannable circuit may considerably affect the operational speed of the circuit device, depending on its design. As noted earlier, often the circuitry providing the scannability may only be used once at the outset of the life cycle of the device, and certainly is rarely to be expected to be used for more than one percent of the device life cycle. Thus, there is a definite trade off to be considered in providing the scannability function for a small period of time, while not overly restricting the operational circuit of the speed when it is used in its “normal” operation, that is, its regular operation when scanning is not being performed. Thus, below are set forth various embodiments within the present inventive scope which provide for scannable circuit devices while increasing operational speed as compared to prior art devices using scannable circuitry.
BRIEF SUMMARY OF THE INVENTION
In one embodiment, there is an integrated circuit device comprising a conductor for receiving a scan data signal. The integrated circuit device further comprises a plurality of storage circuit devices, and each of those storage circuits has a data input and a data output. A first of the plurality of storage circuit devices is coupled to receive the scan data signal at its data input. Moreover, each of the plurality of storage circuit devices other than the first of the plurality of storage circuit devices is coupled to receive at its data input a scan data bit as output from another one of the plurality of storage circuit devices as part of the scan data signal, thereby forming a clocked scan path through the integrated circuit device. The integrated circuit device further comprises a scannable multiplexer circuit having an output coupled to a data input of one of the plurality of storage circuits. The scannable multiplexer circuit comprises a first input for receiving a scan data bit from the scan data signal and a second input for receiving a normal operations data bit. The scannable multiplexer circuit further comprises a first transistor device leaving its source/drain conductive path coupled between the first input and the output of the scannable multiplexer circuit, and having a first threshold voltage, and also a second transistor device having its source/drain conductive path coupled between the second input and the output of the scannable multiplexer circuit, and having a second threshold voltage. The first threshold voltage is larger in absolute value than the second threshold voltage. Other circuits, systems, and methods are also disclosed and claimed.
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“Hybrid Dual-Threshold Design Techniques for High-Performance Processors with Low-Power Features”, Uming Koe, et al., Texas Instruments Incorporated, P. O. Box 660199, M/S 8652, Dallas, Texas 75266-0199, p. 307-311, 1997.
Brady III W. James
Marshall, Jr. Robert D.
Phan Thai
Teleky, Jr. Frederick J.
Teska Kevin J.
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