Scan testing digital logic with differing frequencies of system

Details Scan testing digital logic with differing frequencies of system Scan testing digital logic with differing frequencies of system

1996-11-19

1998-02-10

Beausoliel, Jr., Robert W.

Excavating

371 2232, G01R 3128, G06F 11267

Patent

active

057177023

ABSTRACT:
A boundary scan test circuit that includes Y scan flip-flops serially connected in a sequence from a first scan flip-flop to a Y.sup.th scan flip-flop and clocked with a system clock signal, and circuitry for providing scan input data to the first scan flip-flop synchronously with a test clock signal and for receiving scan output data from the Y.sup.th scan flip-flop synchronously with the test clock signal, wherein the test clock signal and the system clock signal have a test clock period to system clock period ratio that is equal to any fixed integer ratio M.

REFERENCES:
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patent: 5043986 (1991-08-01), Agrawal et al.
patent: 5048021 (1991-09-01), Jarwalo et al.
patent: 5132974 (1992-07-01), Rosales
patent: 5337321 (1994-08-01), Ozaki
patent: 5504756 (1996-04-01), Kime et al.
patent: 5524114 (1996-06-01), Peng

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