Scan test circuit for use in semiconductor integrated circuit

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371 225, G01R 3128

Patent

active

057346607

ABSTRACT:
An object of the present invention is to provide a scan test circuit for use in a semiconductor integrated circuit having a fewer package pins for scan tests.
Scan mode setting and input/output of scan-in and scan-out data are performed by a single-bit bi-directional scan message signal.

REFERENCES:
patent: 4476560 (1984-10-01), Miller et al.
patent: 4855669 (1989-08-01), Mahoney
patent: 4864579 (1989-09-01), Kishida et al.
patent: 5109190 (1992-04-01), Sakashita et al.
patent: 5477493 (1995-12-01), Danbayashi
patent: 5519714 (1996-05-01), Nakamura et al.

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