Scan test apparatus for asynchronous circuitry

Details Scan test apparatus for asynchronous circuitry Scan test apparatus for asynchronous circuitry

1990-01-23

1991-04-16

Wieder, Kenneth

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

371 223, 371 226, 371 251, G01R 3100, G01R 3102

Patent

active

050086189

ABSTRACT:
A scan test cycle is implemented for circuits having sets of elements controlled by mutually asynchronous clock signals by forming a separate scan chain for stimulus and response patterns for the element sets controlled by each clock signal and by performing a separate test sub-cycle for each scan chain.

REFERENCES:
patent: 3761695 (1973-09-01), Eickelberger et al.
patent: 4423509 (1983-12-01), Feissel
patent: 4542509 (1985-09-01), Buchanan et al.
patent: 4580137 (1986-04-01), Fiedler et al.
patent: 4622669 (1986-11-01), Pri-Tal
patent: 4856002 (1989-08-01), Sakashita et al.
patent: 4864579 (1989-09-01), Kishida et al.
patent: 4870345 (1989-09-01), Tomioka et al.
patent: 4879718 (1989-11-01), Sanner
patent: 4897837 (1990-01-01), Isihara et al.
"Hardware Reset of LSSD Logic Chip During System Operation", by IBM, IBM Tech. Disc. Bull., vol. 28, #4, 9/85, pp. 1485-1486.
"Generalized Scan Test Technique for VLSI Circuits", by IBM, IBM Tech. Disc. Bull., vol. 28, #4, 9/85, pp. 1600-1604.

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