1996-12-02
1999-04-06
Beausoliel, Jr., Robert W.
Excavating
39518306, G01R 3128
Patent
active
058927794
ABSTRACT:
A scan test apparatus for operating a test unit according to a test pattern and outputs address information of the test pattern at which a fail takes place, which includes a memory unit for holding circuit information in which scan flip-flops are written at corresponding addresses and a control unit for outputting, in addition to the address information, a scan flip-flop name from the memory unit corresponding to the address information.
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Ishikawa Mitsuaki
Kamada Tadashi
Niijima Hironobu
Ohyama Yasuji
Advantest Corporation
Beausoliel, Jr. Robert W.
Iqbal Nadeem
Kabushiki Kaisha Toshiba
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