Scan-path self-testing circuit for logic units

Details Scan-path self-testing circuit for logic units Scan-path self-testing circuit for logic units

1988-02-26

1989-09-19

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307463, 328137, 328152, 377 77, H03K 1736, H04Q 300, G11C 1900

Patent

active

048684147

ABSTRACT:
For a plurality of logic units which are organized into scan-path groups, a scan-path self-testing circuit is provided which comprises a clock source and a plurality of gates for supplying the clock pulse to the logic units when selectively enabled. To give flexibility to group organization of the logic units, the gates are provided in a one-to-one relationship with the logic units. Bit positions of a register are associated respectively with the gates. A scan path controller selects one of the scan-path groups and writes a logic 1 into the register bit positions which are associated with the logic units of the selected scan-path group.

REFERENCES:
patent: 3461313 (1969-08-01), Hansen
patent: 3721905 (1973-03-01), Newman et al.
patent: 3784978 (1974-01-01), Zola
patent: 3942171 (1976-03-01), Hararzti et al.
R. E. Miller, "Memory Accessing Technique", IBM Technical Disclosure Bulletin, vol. 7, No. 2, Jul. 1964.

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