Scan path circuit with clock signal feedback, for skew avoidance

Details Scan path circuit with clock signal feedback, for skew avoidance Scan path circuit with clock signal feedback, for skew avoidance

1991-10-08

1994-08-09

Beausoliel, Jr., Robert W.

Excavating

H04B 1700

Patent

active

053373219

ABSTRACT:
The scan path circuit includes N number of flip-flops connected in cascade to form a shift register. A first selector and a second selector are connected to each flip-flop to supply the data signal and the clock signal, respectively, to the flip-flop. The first selectors switch the individual data in the normal operation to the scan path test signal and the Q output signals during the test. During the test, the Nth second selector switches the clock signal in the normal operation to the scan path test signal and the second selectors up to the (N-1)th selector switch the clock signals in the normal operation to the clock signals from the output terminals of the next selectors. Thus, clock signals applied to the flip-flops are delayed with respect to those applied to the succeeding flip-flops by a time delay caused by the second selectors, so that the shift register operates reliably irrespective of any clock skew.

REFERENCES:
patent: 4942577 (1990-07-01), Ozaki
patent: 5062110 (1991-10-01), Kobayashi et al.
Joy et al., "Clock Period Minimization with Wave Pipelining", Apr. 1994, IEEE vol. 12, No. 4, pp. 461-470.

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