Scan mechanism for monitoring the state of internal signals of a

Details Scan mechanism for monitoring the state of internal signals of a Scan mechanism for monitoring the state of internal signals of a

1990-11-02

1993-10-12

Atkinson, Charles E.

Excavating

371 223, 371 224, 371 291, G01R 3128

Patent

active

052532550

ABSTRACT:
A VLSI chip debug and production test apparatus that allows an engineer to view the state of hundreds of signals internal to a chip in real-time without probing, which greatly simplifies the isolation of circuit, speed, logic, and microcode bugs. For production testing, it also provides the ability to check the state of these internal signals on a clock-by-clock basis. The mechanism uses a gated XOR-input serial shift-register cell (10), which is stepped out underneath major buses in otherwise unpopulated areas of the chip. Several of these cell groups are linked together to form a scanout path of the desired length, the operation of which is controlled with a single input pin (40). Output data is channeled through a shared output pin (19) to a VLSI tester (16). In the tester (16) the data (19) is checked and accumulated by back-end software over multiple test-loop iterations, and formatted into a readable form.

REFERENCES:
patent: 3937938 (1976-02-01), Matthews
patent: 4862072 (1989-08-01), Harris et al.
patent: 5051944 (1991-09-01), Fetterolf et al.
patent: 5121489 (1992-06-01), Andrews

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