Scan latch and test method therefore

Excavating

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39518306, G06F 1100

Patent

active

057744734

ABSTRACT:
A scan latch comprises a plurality of capture half-latches connected in parallel between an input node and an intermediate node and a release half-latch connected between the intermediate node and a scan output node, each capture half-latch having a control terminal, a capture select terminal and a release select terminal. The control terminals receive a common timing control signal. The capture select terminals receive respective capture select signals for controlling the capture of data inputted to the scan latch. The release select terminals receive respective release select signals for controlling the release of data from the capture half-latches. The scan latch also comprises a control circuit for generating release select signals and capture select signals for selectively controlling the capture half-latches in a normal functional mode of operation. There is also test control circuitry for generating release select signals and capture select signals for selectively enabling the capture half-latches in a test mode. The test control circuitry has a test controller for supplying a sequence of test data bits to the scan latch under the control of the timing control signal, and addressing circuitry for simultaneously addressing both the capture select terminal and release select terminal of each capture half-latch in turn, wherein each capture half-latch can be tested successively.

REFERENCES:
patent: 4742293 (1988-05-01), Koo et al.
patent: 5015875 (1991-05-01), Giles et al.
Standard Search report issued by the European Patent Office Dec. 15, 1994.
IBM Technical Disclosure Bulletin, vol. 33, No. 10A, Mar. 1991, New York US, pp. 112-113, "Four-To-One LSSD Converter".
IBM Technical Disclosure Bulletin, vol. 32, No. 4B, Sep. 1989, New York US pp. 325-330, "Register File With System Logout".

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