Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-06-18
2001-10-23
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
Reexamination Certificate
active
06307529
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a scan drive circuit for a plasma display panel, and more particularly, to a scan drive circuit suitable to an address-while-display driving method.
2. Description of the Related Art
FIG. 1
is a diagram showing a electrode line pattern of a general plasma display panel and
FIG. 2
is a schematic section view of a cell forming a pixel of the plasma display panel shown in FIG.
1
. Referring to the drawings, a general surface-discharge plasma display panel includes address electrode lines A
1
, A
2
, A
3
, . . . and Am, a first dielectric layer
21
, phosphors
22
, scan electrode lines Y
1
, Y
2
, . . . , Yn−1 and Yn (
231
and
232
in FIG.
2
), common electrode lines X (
241
and
242
in FIG.
2
), a second dielectric layer
25
and a protective film
26
. The respective scan electrode lines Y
1
, Y
2
, . . . , Yn−1 and Yn are comprised of a scanning indium tin oxide (ITO) electrode line
231
and a scanning bus electrode line
232
, as shown in FIG.
2
. Similarly, the common electrode lines X are comprised of a common ITO electrode line
241
and a common bus electrode line
242
. A gas for forming plasma is hermetically sealed in a space between the protective film
26
and the first dielectric layer
21
.
The address electrode lines A
1
, A
2
, A
3
, . . . and Am are coated on a lower substrate (not shown) as a first substrate in a predetermined pattern. The first dielectric layer
21
is entirely coated over the address electrode lines A
1
, A
2
, A
3
, . . . and Am. The phosphors
22
are coated on the first dielectric layer
21
in a predetermined pattern. In some cases, the first dielectric layer
21
may not be formed. Instead, the phosphors
22
may be coated over the address electrode lines A
1
, A
2
, A
3
, . . . and Am in a predetermined pattern. The scan electrode lines Y
1
, Y
2
, . . . , Yn−1,
231
and
232
and the common electrode lines X,
241
and
242
are arranged on an upper substrate (not shown) as a second substrate to be orthogonal to the address electrode lines A
1
, A
2
, A
3
, . . . and Am in a predetermined pattern. The respective intersections define corresponding pixels. The second dielectric layer
25
is entirely coated over the scan electrode lines Y
1
, Y
2
, . . . , Yn−1,
231
and
232
and the common electrode lines X,
241
and
242
. The protective film
26
for protecting the panel against a strong electrical field is entirely coated over the second dielectric layer
25
.
A general driving circuit of the plasma display panel is illustrated in FIG.
3
. Referring to
FIG. 3
, the general driving circuit of a plasma display panel
31
includes a controller
34
, a scan drive circuit
35
, a common drive circuit
33
and an address drive circuit
32
. The controller
34
generates a timing control signal corresponding to input image data to apply the same to the scan drive circuit
35
, the common drive circuit
33
and the address drive circuit
32
. The scan drive circuit
35
applies drive signals to the corresponding scan electrode lines Y
1
, Y
2
, . . . and Yn in accordance with the timing control signal generated from the controller
34
. The common drive circuit
33
applies driving signals to the corresponding common electrode lines X in accordance with the timing control signal generated from the controller
34
. The address drive circuit
32
applies an image data signal to the corresponding address electrode lines A
1
, A
2
, . . . and Am in accordance with the timing control signal generated from the controller
34
.
The driving methods generally adopted to the plasma display panel described above are an address/display separation driving method and an address-while-display driving method. In the address/display separation driving method, a reset step, an address step and a sustain discharge step are sequentially performed on all scan electrode lines. On the other hand, in the address-while-display driving method, a reset step, an address step and a sustain discharge step are individually performed on each scan electrode line, irrespective of the arranged order of the scan electrode lines. Thus, according to the address-while-display driving method, a discharge sustain period is longer that in the address/display separation driving method, thereby enhancing the display luminance.
FIG. 4
shows a conventional scan drive circuit adopting the address/display separation driving method in the driving circuit shown in FIG.
3
. Referring to
FIG. 4
, in the conventional scan drive circuit, voltages V
1
, V
2
, V
3
, V
4
and Vg are used, and switching elements S
11
, S
12
, S
13
, S
14
, S
15
, . . . are connected to input ports of the scan electrode lines Y
1
, Y
2
, . . . and Yn, respectively. Here, the number of the switching elements S
11
, S
12
, S
13
, S
14
and S
15
connected to the scan electrode line Y
1
, that is,
5
, is the same as the number of the voltages to be used. This is for individually performing the reset step, the address step and the sustain discharge step for the respective scan electrode lines Y
1
, Y
2
, . . . and Yn of the plasma display panel according to the address-while-display driving method. Thus, in the above-described conventional scan drive circuit, since as many switching elements as the voltages to be used are connected to the input ports of the respective scan electrode lines Y
1
, Y
2
, . . . and Yn, the hardware becomes bulky due to many switching elements. For example, when the number of voltages to be used is 5 and the number of scan electrode lines is 480, 2,400 switching elements are necessary for driving the scan electrode lines. This problem is aggravated for a high definition plasma display panel having many scan electrode lines.
SUMMARY OF THE INVENTION
To solve the above problem, it is an objective of the present invention to provide a scan drive circuit of a plasma display panel which can relatively reduce the number of necessary scan driving switching elements while adopting an address-while-display driving method.
Accordingly, to achieve the above objective, there is provided a scan drive circuit of a plasma display panel in which first and second voltages are applied to the corresponding scan electrode lines during different reset and address periods in accordance with an input timing control signal and a third voltage for a sustain discharge is alternately applied to the corresponding scan electrode lines during a period other than the different reset and address periods, the scan drive circuit including a power switching circuit for outputting two voltages to be simultaneously used among the first, second and third voltages in accordance with the timing control signal, and line switching circuits connected to input ports of the corresponding scan electrode lines, for outputting one of the two voltages input from the power switching circuit to the corresponding scan electrode lines in accordance with the timing control signal.
Therefore, while adopting the address-while-display driving method, the scan drive circuit can relatively reduce the number of scan driving switching elements. In the present invention, only two switching elements are used for each line switching circuit.
REFERENCES:
patent: 6111556 (2000-08-01), Moon
patent: 6144163 (2000-11-01), Amemiya et al.
patent: 6144348 (2000-11-01), Kanazawa et al.
patent: 6144349 (2000-11-01), Awata et al.
Jeon Kwang-hoon
Kang Kyoung-ho
Ryeom Jeong-duk
Hjerpe Richard
Laneau Ronald
Lowe Hauptman & Gilman & Berner LLP
Samsung Display Devices, Ltd.
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