Television – Image signal processing circuitry specific to television – With details of static storage device
Patent
1990-08-02
1994-05-17
Kostak, Victor R.
Television
Image signal processing circuitry specific to television
With details of static storage device
36518904, 348403, H04N 514, H04N 712
Patent
active
053132998
ABSTRACT:
A scan converter control circuit includes first and second memories, each having a data write mode and a data read mode which are selected in response to a switching signal so that the first memory is in the data write mode when the second memory is in the data read mode and the first memory is in the data read mode when the second memory is in the data write mode. A write address counter generates a write address which is to be alternately supplied to the first and second memories and generates a write completion signal when the write address becomes equal to a predetermined count value. A read address counter generates a read address which is to be alternately supplied to the first and second memories and generates a read completion signal when the read address becomes equal to a predetermined count value. A data input controller enables the write address counter in response to a data input signal supplied from an external circuit and disables the write address counter when receiving the write completion signal. A memory switching controller generates the switching signal having a logic value which is changed in response to the write completion signal. A data output controller enables the read address counter in response to the write completion signal and disables the read address counter in response to the read completion signal.
REFERENCES:
patent: 4573080 (1986-02-01), Maze
patent: 4672446 (1987-06-01), Ikeda et al.
patent: 4845669 (1989-07-01), Chappell et al.
patent: 4868656 (1989-09-01), Geiger et al.
patent: 4875196 (1989-10-01), Spaderna et al.
patent: 4893279 (1990-01-01), Rahman et al.
patent: 4918527 (1990-04-01), Penard et al.
patent: 4953020 (1990-08-01), De With
patent: 4958229 (1990-09-01), Guillon et al.
Patent Abstracts of Japan, vol. 7, No. 274 (P-241) Dec. 7, 1983 & JP-A-58 151 670 (Hitachi) Sep. 8, 1983 *the whole document*.
PCT International Publicaiton No. WO 85/02935, Abstract; p. 5, line 14-p. 7, line 32; p. 9, lines 23-35; FIG. 2, Jul. 1985.
Fujitsu Limited
Kostak Victor R.
LandOfFree
Scan converter control circuit having memories and address gener does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Scan converter control circuit having memories and address gener, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scan converter control circuit having memories and address gener will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-881216