Scan cell output latches using switches and bus holders

Details Scan cell output latches using switches and bus holders Scan cell output latches using switches and bus holders

1995-02-28

1997-05-06

Beausoliel, Jr., Robert W.

Excavating

G01R 3128

Patent

active

056278390

ABSTRACT:
A scan cell (95) for use in evaluating the functionality of an electrical circuit includes memory circuitry (Mem 1) for storing test data from a test data path, and a latching circuit (S4, BH) connected to the memory circuitry for receiving and selectively latching the test data stored in the memory circuitry, which latching circuit includes a bus holder circuit (BH).

REFERENCES:
patent: 5005173 (1991-04-01), Martin
patent: 5109190 (1992-04-01), Sakashita et al.
patent: 5377203 (1994-12-01), Khan
patent: 5459737 (1995-10-01), Andrews
patent: 5469473 (1995-11-01), McClear et al.
Bulent Dervisoglu, "IEEE P1149.2 Description and Status Report", IEEE, Sep. 1992, pp. 79-81.
L. Whetsel, "IEEE STD. 1149.1-An Introduction", NEPCON, Feb. 1993, 10 pages.
Unapproved Draft IEEE P1149.2-D2.5, "Extended Digital Serial Subset", IEEE, Aug. 1994, pp. 1-37.
Dilip K. Bhavsar, "Chapter 17. Cell Designs that Help Test Interconnect Shorts," IEEE, 1990 pp. 183-189.
Texas Instruments Incorporated, "TGC1000/TEC1000 5-V CMOS Arrays", Macro Library Summary 1993, pp. 6-19.
Texas Instruments Incorporated, "TGC1000/TEC1000 CMOS Arrays", Design Manual 1993, pp. 3-33.

Affiliated with

Also associated with

Rating

Scan cell output latches using switches and bus holders does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scan cell output latches using switches and bus holders, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scan cell output latches using switches and bus holders will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2138327