Scan-based built-in self test (BIST) with automatic reseeding of

Details Scan-based built-in self test (BIST) with automatic reseeding of Scan-based built-in self test (BIST) with automatic reseeding of

1995-07-25

1996-11-12

Nguyen, Hoa T.

Excavating

371 223, 371 224, 371 225, 371 226, G01R 3128

Patent

active

055747337

ABSTRACT:
A scan chain and method of generating non-successive pseudo-random test patterns for performing a built-in self test (BIST) on a circuit block in an integrated circuit. The scan chain includes a linear feedback shift register (LFSR) cascaded with a shift register. An output of a last storage element of the shift register is fed back in to an input of a first storage element of the LFSR such that the shift register and LFSR form a circular path. A first test pattern is generated in the scan chain when a data string stored in the shift register is shifted through the LFSR. The test pattern is then asserted on inputs of the circuit block. The circuit response is stored in the scan chain, and the scan chain is shifted once more in order to compress the result and generate a second test pattern simultaneously.

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Krasniewski, et al.; Circular Self-Test Path: A low-Cost BIST Technique; ACM/IEEE Design, Automation Conference Proceedings, 1987.
Pomeranz, et al.; A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test; International Test Conference Proceedings, IEEE Computer Society, 1993.
Nadeau-Dostie, et al.; ScanBist A Multi-frequency Scan-Based BIST Method; International Test Conference Proceedings; IEEE Computer Society, 1992.

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