Scaler for synchronous digital clock

Details Scaler for synchronous digital clock Scaler for synchronous digital clock

1990-05-11

1991-11-05

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

377 52, 377 55, 377108, H03K 2138

Patent

active

050635794

ABSTRACT:
A scaler comprising a plurality of flip-flops, varies its frequency division to correct phase by 0.5 clock cycle. Each flip-flop is continuously and synchronously responsive to either a rising or a falling edge of the clock pulses. Normally, the scaler's state transits along one of two loops, which generate output pulses having identical repetition rates. When a control signal is applied, the scaler's state transits from one loop to the other, generating at least one output at an alternative repetition rate. The alternative repetition rate is either lower or higher than the identical repetition rate by an integral number of half cycles of the input clock pulses. Where there are two control signals, a lower or higher alternative repetition rate can be selected. Since the flip-flops are responsive to either edge of the clock pulses without clock gating interruptions, there is no jitter and the scaler's robustness is improved. Also the clock frequency can be effectively halved.

REFERENCES:
patent: 4041403 (1977-08-01), Chiapparoli
patent: 4495630 (1985-01-01), Thompson et al.
patent: 4587664 (1986-05-01), Iida
patent: 4658406 (1987-04-01), Pappas
patent: 4935944 (1990-06-01), Everett
patent: 4942595 (1990-07-01), Baca

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