Scaler architecture for image and video processing

Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal

Reexamination Certificate

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Details

C375S240020, C375S240160, C375S240240

Reexamination Certificate

active

08009729

ABSTRACT:
This disclosure describes a scaler architecture for image and/or video processing. One aspect relates to an apparatus comprising an image processing unit, a memory, and a coder. The memory is configured to store processed image data from the image processing unit. The coder is configured to retrieve the stored, processed image data from the memory. The coder comprises a scaler configured to upscale the retrieved image data from the memory. The coder is configured to encode the scaled image data.

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