Scaled interconnect anodization for high frequency applications

Details Scaled interconnect anodization for high frequency applications Scaled interconnect anodization for high frequency applications

1999-10-29

2001-11-20

Jones, Deborah (Department: 1775)

Stock material or miscellaneous articles

Composite

Of metal

C428S446000, C428S469000, C428S472000, C428S450000, C428S615000, C428S630000, C428S632000, C428S698000, C428S702000, C428S901000, C257S664000, C257S753000, C257S761000, C257S763000, C257S764000, C257S765000, C257S915000

Reexamination Certificate

active

06319616

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to integrated circuit (IC) fabrication, and in particular to a method of fabricating conductive line(s) within the integrated circuit.
BACKGROUND OF THE INVENTION
There is an increasing demand for miniaturization in the integrated circuits industry. This demand has led to an ever constant reduction in separation between conductive lines (e.g., metal lines) in order to reduce integrated circuit size and/or increase density. The reduced spacing between the conductive lines has the undesirable effect of increasing the capacitance of whatever material lies between the conductive lines. This phenomenon is known as capacitive crosstalk.
In the past, overall integrated circuit (IC) performance depended primarily on device properties, however, this is no longer the case. Parasitic resistance, capacitance and inductance associated with interconnections and contacts of an IC are beginning to become increasingly significant factors in IC performance. In current IC technology, the speed limiting factor is no longer device delay, but the resistive-capacitive (RC) delays associated with the conductive interconnections (e.g., metal lines) of the IC.
Conventional ICs typically employ an interconnect structure wherein a first conductive line is adjacent a second conductive line. If the crosstalk or capacitance between the first conductive line and the second conductive line is high, then the voltage on the first conductive line alters or affects the voltage on the second conductive line. This alteration in voltage may result in the IC being inoperable as a result of misinterpreting logic zeros, logic ones and voltage levels, and consequently incorrectly processing binary and/or analog information.
FIGS. 1 and 2
illustrate the relationship between closely spaced conductive lines and capacitive coupling. Conductive lines
30
are adjacent each other and provide necessary electrical connections between devices of an integrated circuit (not shown). Although only three conductive lines
30
are shown for ease of understanding, it is to be appreciated that many thousands or even millions more such conductive lines may exist in the integrated circuit. As noted above, the increasing demand for miniaturization in the integrated circuits industry has led to an ever constant reduction in separation between the conductive lines
30
in order to reduce integrated circuit size. However, the reduced spacing between the conductive lines
30
has the undesirable effect of increasing the capacitance of whatever material lies between the conductive lines
30
to result in capacitive crosstalk between adjacent conductive lines.
A quantity known as pitch (pitch=w+s) is often employed to characterize conductive capacitance crosstalk for adjacent conductive lines used in the integrated circuit industry, where “w” is the cross-sectional width of a conductive line and “s” is the distance of separation between adjacent conductive lines.
FIG. 2
graphically illustrates the capacitance between the conductive lines
30
as a function of physical separation. A reduction in pitch is an ongoing activity in the integrated circuit industry in order to optimize substrate surface area utilization in integrated circuits. The capacitance between the conductive lines
30
labeled C
CL
in
FIG. 2
is shown to increase exponentially as pitch is reduced or as the conductive lines
30
are brought closer together. The increase in capacitive coupling resulting from the conductive lines
30
being brought closer together contributes to capacitive crosstalk between the adjacent conductive lines
30
, respectively.
Since market forces are driving the integrated circuitry towards bringing conductive lines closer together in order to maximize substrate surface utilization, it would be desirable to have a method of fabricating a conductive line structure which facilitates isolation of adjacent conductive lines from one another and lowers capacitive coupling between the conductive lines, respectively, and in turn reduces capacitive crosstalk.
SUMMARY OF THE INVENTION
The present invention provides for a conductive line structure which facilitates mitigation of capacitive cross-talk between conductive lines of an IC. The conductive line structure includes a central conductor and a thin dielectric material substantially covering at least a portion of the central conductor projecting from the surface of a substrate. The structure further includes an outer metal layer which covers the thin dielectric material. Thus a conductive line structure of the present invention provides for a central conductor, and a thin dielectric layer and outer metal layer which symmetrically cover the projecting portion of the conductor. The central conductor is thus substantially shielded from passing noise and induced electromagnetic fields resulting from changing signals therein as well as the central conductor being substantially shielded from externally generated noise and electromagnetic fields.
The present invention provides for a method of making a plurality of the conductive line structures. In making the conductive line structures, conductors are formed on an adhesion layer of a semiconductor wafer. Then the wafer is exposed to an electrolytic agent (e.g., orthophosphoric acid, oxalic acid) and a potential is applied between the wafer and a cathodic material (e.g., platinum, bronze). The wafer is employed as an anode (+) and the cathodic material as a cathode (−) in the anodization process of the present invention. The voltage is applied to substantially transform exposed outer areas of the conductor to a metal oxide (e.g., thin dielectric layer). The transformation of the metal of the conductor to metal oxide continues inwardly in the conductor as long as the voltage is applied. The voltage is applied for a sufficient duration such that substantially all of a second metal layer and a metal adhesion layer are transformed into metal oxide(s). Thereafter, a third metal layer is deposited over the partially complete structure—the third metal layer serving as a shielding/grounding layer of the conductive line structure.
The anodization process of the present invention affords for controlling thicknesses of the metal oxide layer(s) with substantial accuracy. Furthermore, the anodization process provides for forming the metal oxide layer(s) with substantially uniform thickness. The resulting conductive line structure facilitates mitigation of capacitive coupling between adjacent conductive lines. Application of the method of the present invention affords for forming high frequency transmission lines with dimensions scaled in situ during anodization. The present invention thus provides for a method of well defining insulating layer thickness in a conductive line interconnect structure. As a result, frequency characteristics of such an interconnect structure may be calculated. Furthermore, capacitance impedance and working frequency may be predicted for the interconnect structure. It is believed the conductive line interconnect structure of the present invention will be useful in high frequency logic technology applications approaching the gigahertz range and beyond.
In accordance with one particular aspect of the invention, a method of forming a conductive line structure is provided. A first metal layer is formed on a substrate. A second metal layer is formed over the first metal layer. A conductor is formed on the second metal layer. Portions of. the first metal layer, the second metal layer and the conductor are transformed to: first metal oxide, second metal oxide and conductor metal oxide, respectively. The conductor is substantially shielded via the metal oxides from an adjacent conductor.
Another aspect of the present invention provides for a conductive line structure which includes: a substrate; an adhesion layer interposed between a conductor and the substrate; a conductor metal oxide layer substantially covering the conductor, the conductor metal oxide being conductor material

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