Scaleable multicast ATM switch

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

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370389, 370397, 370905, H04L 1228, H04L 1256

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active

057243514

ABSTRACT:
A multicast switch for routing incoming cells having a multicast bit pattern and a priority value, arriving at a plurality of input ports, to one of a plurality of output ports, which includes input port controllers and routing modules. Each of the routing modules routes received cells to an associated one of a plurality of groups of output ports and provides a feedback priority value based on a priority value associated with a lowest priority cell passed to the associated group of output ports. Each of the input port controllers receives the incoming cells, buffers a head-of-line cell, transmits the head-of-line cell to each of the routing modules, stores the multicast bit pattern, compares the priority value of the buffered head-of-line cell with the feedback priority values from each of the routing modules to form a set of comparison values, updates the multicast bit pattern based on the comparison values to form an updated multicast bit pattern, and either retransmits the buffered head-of-line cell, or buffers and transmits a next cell, based on the updated multicast bit pattern.

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patent: 5483521 (1996-01-01), Aramaki
patent: 5509008 (1996-04-01), Genda et al.
Chao, "A Recursive Modular Terabit/Second ATM Switch", IEEE Journal on Selected AReas in Communications, vol. 9, No. 8, Oct. 1991, pp. 1161-1172.
Chao et al., "Design and Analysis of a Large-Scale Multicast Output Buffered ATM Switch", IEEE/ACM Transactions on Networking, vol. 3, No. 2, Apr. 1, 1995, pp. 126-138.
Liew et al., "Comparison of Buffering Strategies for Asymmetric Packet Switch Modules", IEEE Journal on Selected Areas in Communications, vol. 9, No. 3, Apr. 1991, pp. 428-438.

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