Scalar data arithmetic control system for vector arithmetic proc

Details Scalar data arithmetic control system for vector arithmetic proc Scalar data arithmetic control system for vector arithmetic proc

1987-07-02

1990-05-22

Lee, Thomas C.

Boots, shoes, and leggings

36423221, 3642329, 3642511, 3642548, 364736, G06I 15347, G06I 1516, G06I 1200

Patent

active

049282387

ABSTRACT:
A vector arithmetic processor includes a register file for storing an operand of an instruction supplied from a CPU, at least one pointer register for storing address data for the register file, and a scalar control register for storing a signal representing whether an operand is a vector or scalar operand. This at least one pointer register is arranged such that the current value is retained and fed back and the fed back value is used in the second and subsequent cycles when the value of the scalar control register represents a scalar value.

REFERENCES:
patent: 4594682 (1986-06-01), Drimak
patent: 4712175 (1987-12-01), Torii et al.
patent: 4713752 (1987-12-01), Tone
patent: 4739472 (1988-04-01), Hayashi
patent: 4740893 (1988-04-01), Buchholz et al.
patent: 4745547 (1988-05-01), Buchholz et al.
patent: 4760545 (1988-07-01), Imagami et al.
patent: 4794518 (1988-12-01), Mizushima
IBM System Journal vol. 25, No. 1, 1986 "The IBM System/370 Vector Architecture" by W. Buchholz.

Affiliated with

Also associated with

Rating

Scalar data arithmetic control system for vector arithmetic proc does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scalar data arithmetic control system for vector arithmetic proc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scalar data arithmetic control system for vector arithmetic proc will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2138827