Scalable system interrupt structure for a multi-processing syste

Details Scalable system interrupt structure for a multi-processing syste Scalable system interrupt structure for a multi-processing syste

1995-12-18

1997-12-23

Harvey, Jack B.

395737, G06F 946

Patent

active

057014957

ABSTRACT:
An interrupt subsystem within a data processing system is scalable from low-end uni-processor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queueing of interrupts from many sources, and for queueing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.

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