Scalable shader architecture

Details Scalable shader architecture Scalable shader architecture

2007-12-14

2010-12-14

Hsu, Joni (Department: 2628)

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

C345S426000, C345S522000

Reexamination Certificate

active

07852340

ABSTRACT:
A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.

REFERENCES:
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patent: 6940512 (2005-09-01), Yamaguchi et al.
patent: 7015909 (2006-03-01), Morgan III et al.
patent: 7176914 (2007-02-01), Emmot
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patent: 2004-5569 (2004-01-01), None
Eggers, et al. “Simultaneous Multithreading: A Platform for Next-Generation Processors,” IEEE Micro, vol. 17, No. 5, pp. 12-19, Sep./Oct. 1997.
English translation of JP 09-185593 (provided as explanation of relevance).
English translation of JP 09-62852 (provided as explanation of relevance).
English translation of JP 10-69547 (provided as explanation of relevance).
English translation of JP 2004-5569 (provided as explanation of relevance).

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