Boots – shoes – and leggings
Patent
1995-06-29
1997-06-17
Bowler, Alyssa H.
Boots, shoes, and leggings
395 24, 364229, 3642768, 364DIG1, G06F 1700
Patent
active
056405863
ABSTRACT:
A parallel computer architecture supporting neural networks utilizing a novel method of separating a triangular array containing N processing elements on each edge into multiple smaller triangular arrays, each of dimension X and each representing a common building block processor group chip that can be interconnected for various size parallel processing implementations. The group chips are interconnected by a unique switching tree mechanism that maintains the complete connectivity capability and functionality possessed by the original triangular array of dimension N. For a given size K and X, K divisible by X, a triangular array containing K processor elements located on each edge of an equilateral triangular array is partitioned into K/X triangular arrays of dimension X and K(K-X)/2X.sup.2 square processor arrays of dimension X. An algorithm partitions a square array into two triangular arrays, each of dimension X. Assuming K=N and the chosen technology supports the placement of a triangular processor group chip of dimension X on a single chip, the final scalable parallel computing structure for N root tree processors utilizes N.sup.2 /X.sup.2 triangular processor group chips. The partitioning methodology creates a scalable organization of processor elements. An interconnection mechanism preserves the functionality of the original triangular array of dimension N in the implemented structure constructed of multiple triangular arrays of dimension X.
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Delgado-Frias Jose Guadalupe
Pechanek Gerald George
Vassiliadis Stamatis
Bowler Alyssa H.
Harrity John
Hoel John E.
International Business Machines - Corporation
Phillips Steven B.
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