Scalable multimedia platform architecture

Details Scalable multimedia platform architecture Scalable multimedia platform architecture

1996-04-01

1997-06-17

Tung, Kee M.

Computer graphics processing and selective visual display system

Display driving control circuitry

Controlling the condition of display elements

395508, 395520, 345201, G06F 1516

Patent

active

056405430

ABSTRACT:
Scalable platform architecture includes a high bandwidth bus for transmitting data at high bit rates between various video processing subsystems. A graphics processing subsystem, having graphics memory, is coupled to the high bandwidth bus. The graphics processing subsystem is adapted to receive a video memory and to perform video processing when the video memory is received. The high bandwidth bus is provided with expansion connectors for detachably coupling to various subsystems. These subsystems may include a video processing subsystem and a video capture system. The high bandwidth bus is also provided with a bus bridge for coupling the high bandwidth bus to a low bandwidth bus or a central processing unit bus.

REFERENCES:
patent: 5190285 (1993-03-01), Levy et al.
patent: 5315700 (1994-05-01), Johnston et al.
IBM Technical Disclosure Bulletin vol. 32 No. 4B, Sep. 1989, "video system with real-time multi-image capibility and Transparency", pp. 192-193.

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