Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
1998-11-16
2001-10-02
Rose, Robert A. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S287000, C451S486000
Reexamination Certificate
active
06296550
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the fabrication of Semiconductor Wafers, and more specifically to a method of Chemical Mechanical Polishing (CMP) of very large semiconductor wafers of the type used in the fabrication of Integrated Circuits.
DESCRIPTION OF THE PRIOR ART
Integrated Circuits are conventionally fabricated from semiconductor wafers, each wafer contains an array of individual integrated circuit dies. It is of key importance that the wafer be polished to a planar configuration at various stages of the wafer processing stages. This requirement becomes increasingly more difficult to adhere to as the size of the wafer increases.
One of the most serious problems inherent in the CMP process is non-uniformity of the polishing rate over the entire surface of an object to be polished, e.g. a semiconductor wafer. A non-uniform rate of polishing results in not all surface regions of the wafer being polished equally which has a serious detrimental effect on the yield and reliability of the produced semiconductor elements. It is therefore of paramount importance to develop technology which permits further improving the uniformity of the polishing rate over the entire surface of the wafer, a requirement which becomes even more important as the size of the wafer increases.
The present invention addresses the problems of wafer polishing using Chemical Mechanical Planarization for very large wafers.
U.S. Pat. No. 5,575,707 (Talieh et al.) teaches a polishing pad cluster for polishing semiconductor wafers, the pads do not rotate.
U.S. Pat. No. 5,230,184 (Bukhman) teaches a plurality of periodic polishing pads, the pads do not rotate.
When processing a wafer, a conventional wafer clamping arrangement secures a wafer to a wafer cooling pedestal with a circular wafer clamping ring. The clamping ring is used to press the edge of the wafer into the continuous (sealing abutment with the upper surface of the wafer pedestal. A port or opening can be provided to flow a supply of an inert coolant gas, such as argon, to the backside of the wafer, this to improve thermal transfer between the wafer and the heater chuck. This takes advantage of the large thermal mass of the heater chuck relative to the wafer for conducting temperature. In this way, a predictable and consistent temperature is maintained across the wafer surface during wafer processing, and the various process steps that are used to fabricate devices on the wafer surface may be carried out in a reliable manner.
During standard PVD processing, deposition of the metal film on the surface of the semiconductor wafer typically results in the deposition of a metal film on the surface of the clamping ring. This deposition alters the profile (height and inner diameter) of the clamping ring, which in turn results in the metal ring, that is its modified profile, being shadowed on the semiconductor wafer which is being processed. This shadowing has a negative effect on wafer yield and must therefore be restricted or eliminated.
SUMMARY OF THE INVENTION
According to the present invention, a polishing pad cluster is provided for polishing very large semiconductor wafers comprising a plurality of integrated circuit dies. This cluster includes a pad support and a plurality of polishing pads, each of the polishing pads rotating in the plane of the wafer (around the vertical or Z axis) and each polishing pad individually controlled.
A principle object of the present invention is to provide a method of Chemical Mechanical Polishing (CMP) for very large wafers.
Another object of the present invention is to provide extended control over polishing rates of selected areas within the semiconductor wafer being polished.
Another object of the present invention is to maintain polishing uniformity across the wafer for very large wafers.
Another object of the present invention is to maintain process optimization by maintaining tight process parameter control for the processing of very large wafers.
Another object of the present invention is pad condition control and process parameter control across the area of the entire wafer for very large wafers.
In the first embodiment of the present invention the downward pressure of the rotating polishing pad is adjusted via a flexible membrane which is controlled by a pressure cavity. The interface between the the flexible membrane and the polishing pad is formed by ball-bearings.
In the second embodiment of the present invention the downward pressure of the rotating polishing pad is adjusted via a flexible membrane which is controlled by a pressure cavity. The interface between the the flexible membrane and the polishing pad is part of the membrane.
In the third embodiment of the present invention the downward pressure of the rotating polishing pad is controlled by magnets which form part of the rotating polishing pads.
In the fourth embodiment of the present invention the downward pressure of the rotating polishing pad is controlled by one large magnet which forms part of the wafer mount chuck assembly
In the fifth embodiment of the present invention the downward pressure of the rotating polishing pad is controlled by passive mechanical weights which are part of the polishing pads.
REFERENCES:
patent: 2264177 (1941-11-01), Harrington
patent: 2399924 (1946-05-01), Hayward
patent: 5230184 (1993-07-01), Bukhman
patent: 5329734 (1994-07-01), Yu
patent: 5575707 (1996-11-01), Talieh et al.
patent: 5664989 (1997-09-01), Nakata et al.
patent: 5836807 (1998-11-01), Leach
patent: 5934979 (1999-08-01), Talieh
patent: 06252113 (1994-09-01), None
Liu Erzhuang
Pan Yang
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Rose Robert A.
Saile George O.
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