Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
2000-11-16
2003-06-17
Britton, Howard (Department: 2613)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
C375S240290
Reexamination Certificate
active
06580759
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to processing compressed video signals, and more particularly relates to a system and method for scaling an MPEG-2 video decoder.
2. Related Art
The MPEG standards are an evolving set of standards for video and audio compression developed by the Moving Picture Experts Group (MPEG). MPEG-1 was designed for coding progressive video at a transmission rate of about 1.5 million bits per second. It was designed specifically for Video-CD and CD-i media. MPEG-2 was designed for coding interlaced images at transmission rates above 4 million bits per second. The MPEG-2 standard is used for various applications, such as digital television (DTV) broadcasts, digital versatile disk (DVD) technology, and video storage systems.
According to the MPEG-2 standard, a video sequence is divided into a series of GOPs (Group Of Pictures). Each GOP begins with an Intra-coded picture (I picture) followed by an arrangement of forward Predictive-coded pictures (P pictures) and Bi-directionally predictive-coded pictures (B pictures). I pictures are fields or frames coded as a stand-alone still image. P pictures are fields or frames coded relative to the nearest I or P picture, resulting in forward prediction processing. P pictures allow more compression than I pictures through the use of motion compensation, and also serve as a reference for B pictures and future P pictures. B pictures are coded with fields or frames that use the most proximate past and future I and P pictures as a reference, resulting in bi-directional prediction.
As the digital TV market gradually begins to dominate the TV market and other video applications become more desirable, the demand for systems having advanced capabilities for processing MPEG-2 pictures becomes stronger and stronger. The current emerging architecture for processing MPEG-2 pictures, such as that found in DTV set-top boxes and high end digital TV's, typically utilize a combination of a digital signal processing central processing units (DSPCPU), control processors, coprocessors, and software applications. Unfortunately, even with all these resources, advanced audio/visual processing functions tend to consume more computational power than is often available.
One of the key elements in MPEG-2 processing is the MPEG-2 decoder, which converts a bitstream of compressed MPEG-2 data into pixel images. The main components of a generic MPEG-2 decoder
10
are shown in FIG.
1
. There are four functional blocks: a variable length decoder (VLD)
12
, an inverse quantization (IQ) system
14
, an inverse discrete cosine transform system (IDCT)
16
, and a motion compensation (MC) system
18
. Memory
20
is used to store the reference frames. The adder combines the error residuals output from IDCT
16
(path
1
) with motion compensation results (path
2
) to form the final video output
24
. Unfortunately, each of these functional components consume a significant amount of computational power, which drives up the cost, and limits the flexibility of digital video systems using MPEG-2 technology. Accordingly, making a highly efficient, cost effective decoder remains one of the main goals of all electronics manufacturers.
One solution for addressing the processing requirements of MPEG-2 decoders is to provide specialized hardware systems that increase computational power. For example, U.S. Pat. No. 5,903,311, issued to Ozcelik et al. on May 11, 1999, which is hereby incorporated by reference, describes a chip that includes specialized circuits for an MPEG-2 decoder. Unfortunately, while overall hardware costs continue to decrease, the costs involved in designing and building specialized hardware such as this increase the expense of the decoder.
A preferred solution therefore is to implement as much functionality as possible in software, which provides significant cost and flexibility advantages over hardware solutions. In particular, software solutions reduce the need for expensive hardware, such as coprocessors, and will allow multiple video functions to run concurrently on a DSPCPU core. However, software applications tend to run too slow to handle occasions when computationally intensive decoding operations are required. Accordingly, a need exists to provide enhanced systems that will provide inexpensive MPEG-2 decoder solutions while maintaining an acceptable level of video quality.
SUMMARY OF THE INVENTION
This invention overcomes the above-mentioned problems, as well as others, by providing a data processing system that includes at least one scaling application for selectively scaling the complexity of the data processing system. In a first aspect, the invention provides a scalable decoder system, comprising: a processing path for processing video data, having a variable length decoder (VLD), an inverse quantization (IQ) system, and an inverse discrete cosine (IDCT) system arranged in a sequential manner; a scaling application incorporated into the IDCT system for scaling at least one computational process of the IDCT system; and a data pruning system residing within the processing path between the VLD and the IQ system that causes a type of the video data associated with the at least one computational process to be truncated.
In a second aspect, the invention provides a scalable data processing system, comprising: a sequential data path for processing multimedia data, including a first processing module and a second processing module; a scaling application for scaling the second processing module; and a data pruning system positioned prior to the first processing module that causes a portion of the multimedia data associated with the scaling application to be truncated.
In a third aspect, the invention provides a method for scaling a data processing system having a first processing module and a second processing module arranged in a sequential manner, comprising the steps of: inputting data into the data processing system; scaling a computational process in the second processing module; and truncating a predetermined type of data prior to the first processing module that is associated with the computational process in the second processing module.
REFERENCES:
patent: 5668599 (1997-09-01), Cheney et al.
patent: 5903311 (1999-05-01), Ozcelik et al.
patent: 5982431 (1999-11-01), Chung
patent: 6519288 (2003-02-01), Vetro et al.
patent: 0707426 (1996-04-01), None
patent: WO9422108 (1994-03-01), None
patent: WO9636178 (1996-11-01), None
M. Mattavelli et al; “Computational Graceful Degradation for Video Sequence Decoding”, Image Prcessing, 1997, Proceedings, International Conference on Santa Barbara, CA, 10/26-29/1997, pp. 330-333, XP010254175.
Britton Howard
Gross Russell
Koninklijke Philips Electronics , N.V.
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