Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
2000-11-09
2003-09-09
Diep, Nhon (Department: 2613)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
Reexamination Certificate
active
06618445
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to decoding compressed video signals, and more particularly relates to a system and method for scaling an MPEG-2 video decoder.
2. Related Art
The MPEG standards are an evolving set of standards for video and audio compression developed by the Moving Picture Experts Group (MPEG). MPEG-1 was designed for coding progressive video at a transmission rate of about 1.5 million bits per second. It was designed specifically for Video-CD and CD-i media. MPEG-2 was designed for coding interlaced images at transmission rates above 4 million bits per second. The MPEG-2 standard is used for various applications, such as digital television (DTV) broadcasts, digital versatile disk (DVD) technology, and video storage systems.
According to the MPEG-2 standard, an MPEG-2 sequence is divided into a series of GOPs (Group Of Pictures). There are three different types of pictures, with each being essentially a frame of pixels. Each GOP begins with an Intra-coded picture (I picture) followed by an arrangement of forward Predictive-coded pictures (P pictures) and Bi-directionally predictive-coded pictures (B pictures). I pictures are fields or frames coded as a stand-alone still image. P pictures are fields or frames coded relative to the nearest I or P picture, resulting in forward prediction processing. P pictures allow more compression than I pictures through the use of motion compensation, and also serve as a reference for B pictures and future P pictures. B pictures are fields or frames that use the most proximate past and future I and P pictures as a reference, resulting in bi-directional prediction.
As the digital TV market gradually begins to dominate the TV market and other video applications become more desirable, the demand for systems having advanced capabilities for processing MPEG-2 pictures becomes stronger and stronger. The current emerging architecture for processing MPEG-2 data, such as that found in DTV set-top boxes and high end digital TV's, typically utilize a combination of a digital signal processing central processing units (DSPCPU), control processors, coprocessors, and software applications. Unfortunately, even with all these resources, advanced audio/visual processing functions tend to consume more computational power than is often available.
One of the key elements in MPEG-2 processing is the MPEG-2 decoder, which converts a bitstream of compressed MPEG-2 data into pixel images. The main components of a generic MPEG-2 decoder
10
are shown in FIG.
1
. There are four functional blocks: a variable length decoder (VLD)
12
, an inverse quantization (IQ) system
14
, an inverse discrete cosine transform system (IDCT)
16
, and a motion compensation (MC) system
18
. Memory
20
is used to store the reference frames. The adder combines the error residuals output from IDCT
16
(path
1
) with motion compensation results (path
2
) to form the final video output
24
. Unfortunately, each of these functional components consume a significant amount of computational power, which drives up the cost, and limits the flexibility of digital video systems using MPEG-2 technology. Accordingly, making a highly efficient, cost effective decoder remains one of the main goals of all electronics manufacturers.
One solution for addressing the processing requirements of MPEG-2 decoders is to provide specialized hardware systems that increase computational power. For example, U.S. Pat. No. 5,903,311, issued to Ozcelik et al. on May 11, 1999, which is hereby incorporated by reference, describes a chip that includes specialized circuits for an MPEG-2 decoder. Unfortunately, while overall hardware costs continue to decrease, the costs involved in designing and building specialized hardware such as this increase the expense of the decoder.
A preferred solution therefore is to implement as much functionality as possible in software, which provides significant cost and flexibility advantages over hardware solutions. In particular, software solutions reduce the need for expensive hardware, such as coprocessors, and will allow multiple video functions to run concurrently on a DSPCPU core. However, software applications tend to run too slow to handle occasions when computationally intensive decoding operations are required. Accordingly, a need exists to provide enhanced systems that will provide inexpensive MPEG-2 decoder solutions while maintaining an acceptable level of video quality.
SUMMARY OF THE INVENTION
This invention overcomes the above-mentioned problems, as well as others, by providing a scalable decoder system. In a first aspect, the invention includes a decoder system for decoding a compressed video signal having B pictures, comprising: a first processing path that decodes an error residual of the compressed video signal; a second processing path that decodes motion compensation of the compressed video signal; and a filtering system for preventing the error residual associated with B pictures from being decoded by the first processing path. The decoder system may further comprise a system for selectively enabling the filtering system.
In a second aspect, the invention provides a method for decoding compressed video data having different types of coded pictures and outputting displayable pixel data, comprising the steps of: receiving the compressed video data; providing a first and second processing path for processing the compressed video data; identifying pictures of a predetermined type from the compressed video data; and preventing a block associated with at least one of the identified pictures from being processed by the first processing path. The method may be further refined by preventing the processing of only those identified pictures that have a picture characteristic value that is below a predetermined threshold.
In a third aspect, the invention provides a decoder system for decoding compressed video data arranged in a group of pictures, wherein the group of pictures includes at least one B picture, comprising: a processing system for decoding an error residual associated with the group of pictures; and a filtering system for preventing the error residual associated with the B picture from being decoded by the processing system. The decoder system may further include a system for selectively enabling the filtering system.
Accordingly, it is an advantage of the present invention to provide a video processing solution that results in an acceptable level of output degradation in a real-time system that is subject to resource constraints.
It is a further advantage to provide a system and method for efficiently scaling a decoder while maintaining an acceptable level of output quality.
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Mattavelli M et al, “Computational Graceful Degradation For Video Sequence Decoding”, Oct., 1997, pp. 330-333.*
Mattavelli M et al., “Implementing Real-Time Video Decoding On Multimedia Processors By Complexity Prediction Techniques”, 1998 International Conference On Consumer Electronics, Jun. 2-4, 1998, whole document.
Peng Shaomin
Zhong Zhun
Diep Nhon
Gross Russell
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