Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
2001-01-11
2004-04-06
Rao, Andy (Department: 2613)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
C375S240180, C375S240200
Reexamination Certificate
active
06717988
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to processing compressed video signals, and more particularly relates to a system and method for scaling an MPEG-2 video decoder using data pruning.
2. Related Art
The MPEG standards are an evolving set of standards for video and audio compression developed by the Moving Picture Experts Group (MPEG). MPEG-1 was designed for coding progressive video at a transmission rate of about 1.5 million bits per second. It was designed specifically for Video-CD and CD-i media. MPEG-2 was designed for coding interlaced images at transmission rates above 4 million bits per second. The MPEG-2 standard is used for various applications, such as digital television (DTV) broadcasts, digital versatile disk (DVD) technology, and video storage systems.
According to the MPEG-2 standard, a video sequence is divided into a series of GOPs (Group Of Pictures). Each GOP begins with an Intra-coded picture (I picture) followed by an arrangement of forward Predictive-coded pictures (P pictures) and Bi-directionally predictive-coded pictures (B pictures). I pictures are fields or frames coded as a stand-alone still image. P pictures are fields or frames coded relative to the nearest I or P picture, resulting in forward prediction processing. P pictures allow more compression than I pictures through the use of motion compensation, and also serve as a reference for B pictures and future P pictures. B pictures are coded with fields or frames that use the most proximate past and future I and P pictures as references, resulting in bi-directional prediction.
As digital TV gradually begins to dominate the TV market and other video applications become more desirable, the demand for systems having advanced capabilities for processing MPEG-2 pictures becomes stronger and stronger. The current emerging architecture for processing MPEG-2 pictures, such as that found in DTV set-top boxes and high end digital TV's, typically utilize a combination of a digital signal processing central processing units (DSPCPU), control processors, coprocessors, and software applications. Unfortunately, even with all these resources, advanced audio/visual processing functions tend to consume more computational power than is often available.
One of the key elements in MPEG-2 processing is the MPEG-2 decoder, which converts a bitstream of compressed MPEG-2 data into pixel images. The main components of a standard MPEG-2 decoder
10
are shown in FIG.
1
. There are four functional blocks: a variable length decoder (VLD)
12
, an inverse quantization (IQ) system
14
, an inverse discrete cosine transform system (IDCT)
16
, and a motion compensation (MC) system
18
. Memory
20
is used to store the reference frames. The adder
22
combines the error residuals output from IDCT
16
with motion compensation results to form the final video output
24
. Unfortunately, each of these functional components consume a significant amount of computational power, which drives up the cost, and limits the flexibility of digital video systems using MPEG-2 technology. Accordingly, making a highly efficient, cost effective decoder remains one of the main goals of all electronics manufacturers.
One solution for addressing the processing requirements of MPEG-2 decoders is to provide specialized hardware systems that increase computational power. Unfortunately, while overall hardware costs continue to decrease, the costs involved in designing and building specialized hardware such as this increase the expense of the decoder.
A preferred solution therefore is to implement as much functionality as possible in software, which provides significant cost and flexibility advantages over hardware solutions. In particular, software solutions reduce the need for expensive hardware, such as coprocessors, and will allow multiple video functions to run concurrently on a DSPCPU core. However, software applications tend to run too slow to handle occasions when computationally intensive decoding operations are required. Accordingly, a need exists to provide enhanced software systems that will provide inexpensive MPEG-2 decoder solutions while maintaining an acceptable level of video quality.
SUMMARY OF THE INVENTION
This invention overcomes the above-mentioned problems, as well as others, by providing a decoder having a scalable IDCT system that selects a unique data pruning pattern to meet a complexity budget allocated to the IDCT. In a first aspect, the invention provides a scalable IDCT system, comprising: a plurality of scaling algorithms; a system for receiving a complexity budget; a system for selecting one of the plurality of scaling algorithms based on the received complexity budget; and a system for processing an inputted block of discrete cosine transform (DCT) data using the selected scaling algorithm.
In a second aspect, the invention provides a video decoder system, comprising: a system for determining a complexity level based on an inputted complexity budget; and an IDCT system that selects a scaling algorithm from a plurality of scaling algorithms, wherein the selected scaling algorithm corresponds to the determined complexity level.
In a third aspect, the invention provides a method of scaling the processing of discrete cosine transform (DCT) blocks by an IDCT system in a video decoder, comprising the steps of: providing a complexity budget to the IDCT system; selecting one of a plurality of scaling algorithms based on the complexity budget; and processing at least one DCT block using the selected scaling algorithm.
In a fourth aspect, the invention provides a system for processing DCT data, comprising: a plurality of scaling algorithms, each capable of processing an inputted block of DCT data; a system for receiving a complexity budget; and a system for implementing one of the plurality of scaling algorithms to meet the received complexity budget.
In each of the above-mentioned aspects, each block of DCT data is comprised of DCT coefficients, and each of the plurality of scaling algorithms causes a unique pattern of DCT coefficients to be selected for processing. Moreover, each unique pattern of DCT coefficients selected for processing may comprise a rectangular arrangement of DCT coefficients having a predetermined number of rows and columns.
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Belk Michael E.
Koninklijke Philips Electronics , N.V.
Parsons Charles E
Rao Andy
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