Pulse or digital communications – Spread spectrum
Reexamination Certificate
2000-05-09
2001-11-27
Vo, Don N. (Department: 2631)
Pulse or digital communications
Spread spectrum
C708S253000
Reexamination Certificate
active
06324205
ABSTRACT:
FIELD OF THE INVENTION
The present disclosure relates to spread spectrum communication systems and, in particular, to generation of long code sequences in spread spectrum communication systems.
BACKGROUND OF THE INVENTION
Long code sequences are widely used in communication systems to spread and despread the data-modulated carrier. Both 1X and 3X long code sequences are used in spread spectrum communication systems.
A 3X long code sequence is typically generated from its 1X counterpart. For example, the method proposed by Laird et al. (see “Additional information on Motorola 3X long code generator,” by K. Laird, J. Chen, and F. Zhou (Motorola), TR45.5.3.1/99.04.20.07, April 1999, Savannah, Ga.) as well as that proposed by Ramesh et al. (see “A modified long code generation method for spreading rate 3,” by N. Ramesh and Q. Li (Lucent), TR45.5.3.1/99.04.20.08, April 1999, Savannah, Ga.) entail taking shifted versions of the 1X long code at 1.2288 Mchips/sec and interlacing them to generate a 3X long code sequence at 3.6864 Mchips/sec. However, the auto-correlation function of the 3X long code sequences generated by either of the above methods are prohibitively high, leading to undesirable interference problems.
In the method proposed by Laird et al., the magnitude of auto-correlation of the generated 3X sequence can be varied by the degree of shift of the starting 1X sequence thus allowing for improvement in the auto-correlation magnitude. In the method proposed by Ramesh, however, the shift values are unknown, leading to unacceptable auto-correlation levels.
In a publication entitled “Long code generators for 3X systems” (see R. T. Derryberry and Mohit K. Prasad, “Long code generators for 3X systems,” TR45.5.3.1 Adhoc/99.04.28.0x, Apr. 28, 1999, Teleconference), the authors describe a scalable method for generating long code sequences. Because the system is scalable, the number of long code generators scales linearly with the type of system in use. For example, the method generates 3 long code sequences for 3X systems, 6 long code sequences for 6X systems, etc. However, the method described by Derryberry et al. requires that multiple long code states be initialized or exchanged during signaling.
Accordingly, it would be advantageous to generate a long code sequence which is not subject to the infirmities of the existing methods and systems.
SUMMARY OF THE INVENTION
A scalable method for generating a KX long code sequence—where K is an integer multiple of 3—includes: (i) generating a preferred pair of m-sequences b(d) and b′(D) each of which is a 1X long code sequence of length N, wherein N=2
n
−1; (ii) forming sequence [b(d)+b′(D)] by modulo
2
adding sequences b(d) and b′(D); (iii) delaying the sequence b′(D) by a predefined amount of time by each of [1, 2, 3 . . . (K−4),(K−3)] times to thereby form (K−3) delayed sequences Db′(D), D
2
b′(D), D
3
b′(D) . . . D
(K−4)
b′(D), D
(K−3)
b′(D); (iv) modulo
2
adding the sequence b(d) to each of the (K−3) delayed sequences to thereby form (K−3) sequences [b(D)+Db′(D)], [b(D)+D
2
b′(D)], [b(D)+D
3
b′(D)], . . . , [b(D)+D
(K−4)
b′(D)], [b(D)+D
(K−3)
b′(D)]; (v) generating a KX clock signal whose frequency is K times that of a clock signal used to generate the 1X sequences b(d) and b′(d); (vi) recurrently within each K transitions of the KX clock sequentially setting an with bit of the KX sequence to an with bit of one of the K sequences b(D), [b(D)+b′(d)], b′(D), [b(D)+Db′(D)], [b(D)+D
2
b′(D)], [b(D)+D
3
b′(D)], . . . , [b(D)+D
(K−4)
b′(D)], [b(D)+D
(K−3)
b′(D)] sequentially.
When K is equal to 3 and N is equal to 42, the method, in accordance with one embodiment includes: (i) generating a preferred pair of m-sequences b(D) and b′(D) each being of the length (2
42
−1); (2) forming the sequence [b(D)+b′(d)] by performing modulo
2
addition on sequences b(d) and b′(d); (3) setting the (i+1)th bit of sequence 3X, where i is a multiple of 3 and varies between 0 and 42, equal to (i+1)th bit of the sequence b(D) at every (i+1)th transition of a clock signal running at the rate of 3.6864 Mchips/s; (4) setting the (i+2)th bit of sequence 3X equal to the (i+1)th bit of the sequence [b(D)+b′(D)] at every (i+2)th transition of the clock signal; (5) setting the (i+3)th bit of sequence 3X equal to the (i+1)th bit of the sequence b′(D) at every (i+2)th transition of the clock signal.
A system for generating a 3X long Code sequence, in accordance with one embodiment, includes two 1X long code sequence generators for generating the preferred pairs b(D) and b′(D), a modulo
2
adder for generating sequence [b(D) and b′(D)] and a 3-input multiplexer. The signals generated by sequences b(d), b′(D) and [b(D)+b′(D)] are coupled to input terminals of the multiplexer, while a 2-bit SELECT signal operating at the rate of 3.6864 Mchips/s is applied to the select input terminal of the multiplexer.
During every three transitions of signal SELECT a bit respectively from the three sequences b(D), b′(D) and [b(D)+b′(d)], is passed from the multiplexer's input terminal to its output terminal, thereby generating the 3X long code sequence at the output terminal of the multiplexer.
When K is equal to 6 and N is equal to 42, the method includes: (1) generating a preferred pair of m-sequences b(D) and b′(D) each being of the length (2
42
−1); (2) forming the sequence [b(D)+b′(d)] by performing modulo
2
addition on sequences b(d) and b′(d); (4) forming three delayed sequences of b′(D), namely sequences Db′(D), D
2
b′(D) and D
3
b′(D) (5) modulo
2
adding sequence b(D) with each of the delayed b′(D) sequences to thereby generate sequences [b(D)+Db′(d)], [b(D)+D
2
b′(d)], [b(D)+D
3
b′(d)]; (6) setting the (i+1)th bit of sequence 6X, where i is a multiple of 6 and varies between 0 and 42, equal to (i+1)th bit of the sequence b(D) at every (i+1)th transition of a clock signal running at the rate of 7.3728 Mchips/s; (7) setting the (i+2)th bit of sequence 6X equal to the (i+1)th bit of the sequence [b(D)+b′(D)] at every (i+2)th transition of the clock signal; (8) setting the (i+3)th bit of sequence 6X equal to the (i+1)th bit of the sequence b′(D) at every (i+3)th transition of the clock signal; (9) setting the (i+4)th bit of sequence 6X equal to the (i+1)th bit of the sequence [b(D)+Db′(D)] at every (i+4)th transition of the clock signal; (10) setting the (i+5)th bit of sequence 6X equal to the (i+1)th bit of the sequence [b(D)+D
2
b′(D)] at every (i+5)th transition of the clock signal; and (11) setting the (i+6)th bit of sequence 6X equal to the (i+1)th bit of the sequence [b(D)+D
3
b′(D)] at every (i+6)th transition of the clock signal.
REFERENCES:
patent: 5068872 (1991-11-01), Schroter
patent: 5629955 (1997-05-01), McDonough
patent: 5790891 (1998-08-01), Gold et al.
patent: 5796776 (1998-08-01), Lomp et al.
Laird, et a; “Additional Information on the Motorola 3X Long Code Generator”; Data Sheet; TR45.5.3.1/99.04.20.07, Apr., 1999, pp. 1-4.
Ramesh, et al.; “A Modified Long Code Generation Method for Spreading Rate 3”; 1999, Data Sheet TR45.5.3.1/99.04.20.08, Apr. 20, 1999, pp. 1-6.
Massey. “Shift-Register Synthesis and BCH Decoding”; IEEE Transactions on Information Theory, vol.
Heid David W.
Skjerven Morrill & MacPherson LLP
Sony Corporation
Vo Don N.
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