Scalable link-level flow-control for a switching device

Details Scalable link-level flow-control for a switching device Scalable link-level flow-control for a switching device

2007-12-04

2007-12-04

Jain, Raj K (Department: 2616)

Multiplex communications

Data flow congestion prevention or control

Control of data admission to the network

C370S230000, C370S230100, C370S232000, C370S235000, C370S352000, C370S353000, C370S354000, C370S355000, C370S356000

Reexamination Certificate

active

10357534

ABSTRACT:
The present invention discloses a scalable flow-control mechanism. In accordance with the present invention, there is provided a switching device for transporting packets of data, the packets being received at the switching device based on flow-control information, the device comprising a memory for storing the packets, a credit counter coupled to the memory for counting a credit number of packets departing from the memory, and a scheduler unit coupled to the credit counter for deriving the flow-control information in response to the credit number. Moreover, a switching apparatus and a method for generating flow-control information is disclosed.

REFERENCES:
patent: 7023857 (2006-04-01), Chiussi et al.
patent: 2002/0044546 (2002-04-01), Magill et al.
G. Kornaros et al. “Implementation of ATLAS I: a Single-Chip ATM Switch with Backpressure” in Proc. IEEE Hot Interconnects VI Symposium, Stanford, California, USA Aug. 13-15, 1998, pp. 85-96.
C. Minkenberg and T. Engbersen, “A Combined Input- and Output-Queued Packet-Switch System Based on PRIZMA Switch-on-a-Chip Technology” by in IEEE Commun. Mag., vol. 38, No. 12, Dec. 2000, pp. 70-77.

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