Scalable IP edge router

Details Scalable IP edge router Scalable IP edge router

2000-05-09

2003-08-05

Meky, Moustafa M. (Department: 2154)

Electrical computers and digital processing systems: multicomput

Computer-to-computer data routing

Prioritized data routing

C709S238000, C370S351000

Reexamination Certificate

active

06604147

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to data communications routers, and more particularly, to a scalable architecture for enterprise-class data communications routers.
BACKGROUND OF THE INVENTION
Enterprise-class data communications networks serve a varied class of users having both local-area and wide-area networking needs.
FIG. 1
depicts a typical enterprise class network
102
. Enterprise-class routers are typically deployed at two positions in the network. An enterprise backbone router (EBR)
104
provides data packet routing among a plurality of local area subnetworks (intranets). The EBR functions primarily to provide efficient routing of packets travelling between the intranets.
In addition to the EBR, an enterprise edge router (EER)
100
functions primarily to concentrate data traffic arriving from one or more interconnected enterprise intranets so that this traffic may be efficiently forwarded over T
1
or other wide area data communications facilities to an access provider edge router
114
. The access provider edge router
114
typically routes enterprise traffic to one or more internet service providers (ISPs) for transport to other networks.
In addition to concentrating data traffic from a number of interconnected intranets, the EER
102
may provide a variety of value-added functions including but not limited to packet recognition, packet filtering, packet classification for quality of service (QoS) features, internet protocol (IP) address look-up and translation, buffer management, packet scheduling, data encryption and compression, load balancing, traffic monitoring, traffic billing and multicast support. The bundle of such functions provided in a given enterprise application will depend on the size and nature of the application. For example, an enterprise network deployed in a public school may comprise a small number of intranets with basic features and low-bandwidth concentration (often, for example, at fractional T
1
rates). In sharp contrast, an enterprise network deployed by a large commercial enterprise such as a financial institution may comprise a large intranet base with more sophisticated features and with high-bandwidth concentration (often at T
3
and OC
3
rates). Also, intranet architectures and data protocols will vary widely with enterprise class. For example, banking networks may support “legacy” protocols such as IPX and SNA, while “internet company” networks may be based entirely on IP protocols.
FIG. 2
illustrates a typical architecture used currently for edge routers. The edge router
200
of
FIG. 2
includes a central processing unit (CPU)
206
, a memory
208
, and one or more line interface cards
212
, each interconnected by a bus
216
. Each line interface card
212
further includes a local memory
213
.
In the edge router
200
of
FIG. 2
, an arriving packet is received at a line interface card
212
and stored in an associated local memory
213
. The line interface card
212
then signals the CPU
206
that a packet has arrived for processing. In response, the CPU
206
retrieves the stored-packet and places it in the memory
208
. The CPU
206
processes the packet (for example, by computing a “next hop” address for the packet on the basis of the packet's end destination address). After the packet is processed, the CPU
206
selects a line interface card
212
to be used to transmit the processed packet from the edge router
204
, retrieves the stored packet, and transfers the retrieved packet to the selected line interface card
212
for transmission to the next hop address.
Because the CPU
206
may be programmed to perform a variety of functions, the router architecture illustrated in
FIG. 2
provides significant flexibility. However, router performance and capacity will be strongly dictated by the performance characteristics of individual router components such as the CPU
206
, the memory
208
and the bus
216
. As a result, to serve a variety of application environments, router manufactures employing this architecture are generally forced to provide a variety of different router products. This creates inefficiency for the router manufacturers, as well as added cost for enterprises that are forced to replace routers as their networks grow in size and their feature requirements change.
Accordingly, it would be desirable to develop a more flexible router architecture that allows a variety of enterprise network feature and capacity requirements to be more easily met.
SUMMARY OF THE INVENTION
Improved flexibility in features and performance is achieved by an improved architecture for enterprise data communications routers. According to a first embodiment of the invention, the architecture comprises a buffer for storing data packets, a processing engine for processing information associated with the stored data packets, and one or more line interface cards (LICs) each having one or more ports for receiving and transmitting data packets. Source LICs receive data packets at source ports, store received packets in the buffer, and transmit packet tags incorporating a selected subset of information from the data packets to the processing engine for processing. Packet storage and tag processing are accomplished largely in parallel for improved router efficiency.
The processing engine processes and transmits the processed packet tags to destination LICs. The destination LICs, in response to information contained in processed tags, retrieve associated data packets from the buffer, modify the retrieved data packets, and deliver the modified data packets to associated LIC destination ports.
In a second embodiment of the invention, the processing engine further includes one or more serially arranged pipeline processing modules (PPMs) to process the header information. The serially arranged PPMs are each programmed to perform a dedicated processing function. In addition, a system controller is coupled to the serially arranged PPMs to receive and process header information associated with control and signaling data packets, and to dynamically update stored program control software in the serially arranged PPMs.


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patent: 6262983 (2001-07-01), Yoshizawa et al.
patent: 6292489 (2001-09-01), Fukushima et al.
patent: 6292836 (2001-09-01), Teraoka
patent: 6353614 (2002-03-01), Borella et al.
patent: 6421734 (2002-07-01), Nessett et al.
patent: 6510164 (2003-01-01), Ramaswamy et al.

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