Scalable high performance antifuse structure and process

Details Scalable high performance antifuse structure and process Scalable high performance antifuse structure and process

2005-09-13

2005-09-13

Kang, Donghee (Department: 2811)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Using structure alterable to conductive state

C438S467000, C438S600000, C438S647000, C257S050000, C257S209000, C257S529000, C257S530000

Reexamination Certificate

active

06943065

ABSTRACT:
Systems and methods are provided for a scalable high-performance antifuse structure and process that has a low RC component, a uniform dielectric breakdown, and a very low, effective dielectric constant (keff) such that a programming pulse voltage is scalable with Vdd. One aspect of the present subject matter is an antifuse device that is positioned or coupled between a first metal level and a second metal level. One embodiment of the antifuse device includes a porous antifuse dielectric layer, and at least one injector Silicon-Rich-Insulator (SRI) layer in contact with the porous antifuse dielectric layer. In one embodiment, the porous antifuse dielectric layer includes SiO2formed with air-filled voids. In one embodiment, the at least one injector SRI layer includes two injector Silicon-Rich-Nitride layers that sandwich the porous antifuse dielectric layer. Other aspects are provided herein.

REFERENCES:
patent: 4962058 (1990-10-01), Cronin et al.
patent: 5110754 (1992-05-01), Lowrey et al.
patent: 5250459 (1993-10-01), Lee
patent: 5404029 (1995-04-01), Husher et al.
patent: 5639684 (1997-06-01), Kwok
patent: 5811870 (1998-09-01), Bhattacharyya et al.
patent: 5834824 (1998-11-01), Shepherd et al.
patent: 5903041 (1999-05-01), La Fleur et al.
patent: 5962910 (1999-10-01), Hawley et al.
patent: 5969983 (1999-10-01), Thakur et al.
patent: 5973380 (1999-10-01), Cutter et al.
patent: 6016001 (2000-01-01), Sanchez et al.
patent: 6069064 (2000-05-01), Cutter et al.
patent: 6077792 (2000-06-01), Farrar
patent: 6084814 (2000-07-01), Casper et al.
patent: 6088282 (2000-07-01), Loughmiller et al.
patent: 6097077 (2000-08-01), Gordon et al.
patent: 6146925 (2000-11-01), Dennison
patent: 6252293 (2001-06-01), Seyyedy et al.
patent: 6284675 (2001-09-01), Jin et al.
patent: 6288437 (2001-09-01), Forbes et al.
patent: 6291871 (2001-09-01), Dennison
patent: 6323536 (2001-11-01), Cutter et al.
patent: 6344373 (2002-02-01), Bhattacharyya et al.
patent: 6351425 (2002-02-01), Porter
patent: 6383924 (2002-05-01), Farrar et al.
patent: 6423582 (2002-07-01), Fischer et al.
patent: 6444558 (2002-09-01), Cutter et al.
patent: 6456149 (2002-09-01), Cutter et al.
patent: 6458630 (2002-10-01), Daubenspeck et al.
patent: 6495395 (2002-12-01), Reinberg
patent: 6498056 (2002-12-01), Motsiff et al.
patent: 6509623 (2003-01-01), Zhao
patent: 6525399 (2003-02-01), Cutter et al.
patent: 6541811 (2003-04-01), Thakur et al.
patent: 6582512 (2003-06-01), Geusic et al.
patent: 6630724 (2003-10-01), Marr
patent: 6657277 (2003-12-01), Hsieh
patent: 6674667 (2004-01-01), Forbes
patent: 2002/0182837 (2002-12-01), Daubenspeck et al.
patent: 2003/0042534 (2003-03-01), Bhattacharyya
patent: 2003/0071324 (2003-04-01), Motsiff et al.
patent: 2003/0181018 (2003-09-01), Geusic et al.
“CRC handbook of chemistry and physics”,49th edition, CRC Press, Cleveland, Ohio, (1968-1969),E-61.
Asoh, H , “Fabrication of ideally ordered anodic porous alumina with 63 nm hole periodicity using sulfuric acid”,Journal of Vacuum Science&Technology B(Microelectronics and Nanometer Structures), 19(2), (Mar. 2001),569-72.
Beauvais, J , et al., “Nano-Imprint Lithography using Masks Fabricated by SIDWEL Process”,Tenth Canadian Semiconductor Technology Conference Ottawa, Canada, (Aug. 13-17, 2001).
Bhattacharyya, A., “Physical & Electrical Characteristics of LPCVD Silicon Rich Nitride”,ECS Technical Digest, J. Electrochem, Soc., 131(11), 691 RDP, New Orleans,(1984),469C.
Chou, S Y., et al., “Imprint lithography with sub-10 nm feature size and high throughput”,Microelectronic Engineering, 35(1-4), (Feb. 1997),237-40.
Chou, S Y., et al., “Sub-10 nm imprint lithography applications”,Journal of Vacuum Science&Technology B(Microelectronics and Nanometer Structures), 15(6), (Nov.-Dec. 1997),2897-904.
Devasahayam, A J., et al., “Material Properties of Ion Beam Deposited Oxides for the Opto-Electronic Industry”,Tenth Canadian Semiconductor Technology Conference, Ottawa, Canada, (Aug. 13-17, 2001).
Jeng, Shin-Puu , et al., “A planarized multilevel interconnect scheme with embedded low-dieletric-constant polymers for sub-quarter-micron applications”,VLSI Technology, 1994, Digest of Technical Papers. 1994 Symposium on, Jun. 7-9, 1994,73-74.
Jin, C , et al., “Evaluation of ultra-low-k dielectric materials for advanced interconnects”,Journal of Electronic Materials, 30(4), (Apr. 2001),284-9.
Jurczak, M , “SON (silicon on nothing)—a new device architecture for the ULSI era”,VLSI Technology, 1999, Digest of Technical Papers, 1999 Symposium on , Jun. 14-16, 1999,29-30.
Kingery, W D., “Introduction to ceramics”, New York, Wiley, (1963),262-263.
Kittel, C A., “Introduction to Solid State Physics”,3rd Edition, J. Wiley&Sons, (1967),25.
Mizushima, I., et al., “Empty-space-in-silicon technique for fabricating a silicon-on-nothing structure”,Applied Physics Letters, 77(20), American Institute of Physics, NY,(Nov. 13, 2000),3290-3292.
Morey, George W., “The properties of glass”,Published New York, Reinhold publishing corporation, Series Monograph series(American Chemical Society) ; No. 77., (1938),12, 48-49.
Nichols, F A., “Surface-(interace) and volume-diffusion contributions to morphological changes driven by capillarity”,Transactions of the American Institute of Mining, Metallurgical and Petroleum Engineers, 233(10), (1965),1840-8.
Sato, T , “A new substrate engineering for the formation of empty space in silicon (ESS) induced by silicon surface migration”,International Electron Devices Meeting 1999, Technical Digest, (1999),517-20.
Sato, T , “Trench transformation technology using hydrogen annealing for realizing highly reliable device structure with thin dielectric films”,1998 Symposium on VLSI Technology Digest of Technical Papers, (1998),206-7.
Treichel, H , “Low dielectric constant materials”,Journal of Electronic Materials, 30(4), (Apr. 2001),290-8.
Wojcik, J , et al., “Characterization of Silicon Oxynitride Thin Films Deposited by ECR-PECVD”,Tenth Canadian Semiconductor Technology Conference, Ottawa, Canada, (Aug. 13-17, 2001).
Zhang, F , “Nanoglass/sup TM/ E copper damascene processing for etch, clean, and CMP”,Proceedings of the IEEE 2001 International Interconnect Technology Conference, (2001),57-9.

Affiliated with

Also associated with

Rating

Scalable high performance antifuse structure and process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scalable high performance antifuse structure and process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scalable high performance antifuse structure and process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3405741