Scalable high performance 3D graphics

Details Scalable high performance 3D graphics Scalable high performance 3D graphics

2008-05-27

2008-05-27

Tung, Kee M. (Department: 2628)

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

C709S251000, C345S530000

Reexamination Certificate

active

07379067

ABSTRACT:
A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

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