Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-08-17
2002-12-17
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S698000, C257S691000, C257S773000, C257S659000, C257S774000
Reexamination Certificate
active
06495911
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to information processing systems and more particularly to a methodology and implementation for signal transmission in an integrated circuit carrier package.
RELATED APPLICATIONS
Subject matter disclosed and not claimed herein is disclosed and claimed in one or more of the following related co-pending applications, which are assigned to the assignee of the present application and included herein by reference:
Ser. No. 09/640,539;
Ser. No. 09/640,538; and
Ser. No. 09/640,512.
BACKGROUND OF THE INVENTION
In digital computer assemblies, including integrated circuit (IC) or chip carrier packages, it has become common practice over the years to sandwich a logic signal (SIG) transmission line between two reference planes, i.e. between a power (VDD) reference plane and a power return ground (GND) reference plane, while transmitting the logic signal from a driver circuit to one or more receiver circuits. With regard to a chip carrier in particular, the minimum that a chip package carrier must supply to a chip mounted thereon is one or more power supply voltages (VDD), one or more ground returns (GND), and a sufficient number of signal (SIG) lines. Currently these requirements are furnished by means of sets of separate planes for VDD, SIG and GND connections to the mounted chip. In other words, a plane of signal lines is defined on a SIG plane that is positioned or “sandwiched” between a GND plane and a voltage VDD plane. The semiconductor chip sits on top at the center of the package. The signal lines radiate outwardly from the chip area and connect to the card area below the carrier “sandwich” which is made up of the three reference planes. De-coupling capacitors on the chip and the chip carrier between VDD and GND supply the electrical charge current at the low source inductance needed to drive fast transitions into the signal lines at the chip source end. While this construction has been satisfactory in the past, increasing operating frequencies of systems and chips has created problems with regard to signal isolation and noise immunity.
Thus there is a need for an improved chip carrier package design which provides greater signal isolation and noise immunity in systems and chips having high operating frequencies.
SUMMARY OF THE INVENTION
A method and implementing system are provided in which a tri-plate structure is arranged to include three substrate layers surrounding an integrated circuit chip which is mounted thereon. In an exemplary embodiment, the tri-plate structure includes a middle or signal layer, a first outer layer or top layer, and a second outer layer or bottom layer. The first and second outer layers are positioned on each side of the signal layer. The three layers are arranged on electrically insulative material and the three layers are sandwiched together to form a chip carrier. The chip is mounted on the middle layer or signal (SIG) layer and extends through an opening in the top layer. The middle signal layer includes bundles or groups of printed circuit conductors or lines to carry signals between the chip and the edges of the carrier device. The first outer layer includes electrically isolated and separate conducting areas or segments which are held at different system potentials, for example at ground (GND) and VDD power potential levels. The separate conducting areas on the top layer are separated by air gaps or by insulative material to provide adequate electrical isolation. The separate areas are arranged on the first outer layer relative to the signal conductors in the middle layer such that signal lines from the chip to the outer edges of the chip carrier in the middle layer are positioned under areas of ground potential in the first outer layer and above the grounded second outer layer which is positioned below the signal layer in the carrier device. Thus, each group of signal conductors in the middle layer between the chip and the outer edges of the carrier have a ground potential area or segment above each signal conductor group and also a ground potential layer below each signal conductor group. The tri-plate structure thus formed provides system electromagnetic radiation isolation and enhanced noise isolation and signal integrity. In the example, ground areas in the top layer are connected to the bottom ground potential layer through vias which pass through the middle layer. Also, vias are used to connect de-coupling capacitors between VDD areas in the top layer and the ground potential bottom layer.
REFERENCES:
patent: 5925925 (1999-07-01), Dehaine et al.
patent: 6359341 (2002-03-01), Huang et al.
Buffet Patrick H.
Clouser Paul Lee
Neal Danny Marvin
International Business Machines - Corporation
McBurney Mark E.
Talbott David L.
Thai Luan
Wilder Robert V.
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