Scalable flash EEPROM memory cell and array

Static information storage and retrieval – Floating gate – Particular connection

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Details

36518515, 36518528, 36518503, G11C 1604

Patent

active

058569430

ABSTRACT:
A scalable flash EEPROM cell has a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate has a first portion over the select gate and insulated therefrom, and a second portion over a second portion of the channel and over the source, and is between the select gate and the source. A control gate is over the floating gate and is insulated therefrom. A memory array using this memory cell is also disclosed.

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