Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2011-04-05
2011-04-05
Nguyen, Viet Q (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185180, C365S185240, C365S185280, C365S218000
Reexamination Certificate
active
07920424
ABSTRACT:
A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage VPPacross the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.
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Cosmin A. Peter
Georgescu Sorin S.
Bever Hoffman & Harms LLP
Hoffman E. Eric
Nguyen Viet Q
Semiconductor Components Industries L.L.C.
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