Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2011-08-23
2011-08-23
Ngo, Chuong D (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C382S262000
Reexamination Certificate
active
08005881
ABSTRACT:
A rank order filter and instantiation thereof in programmable logic is described. A maximum filter core frequency is determined for an input sampling frequency, a filter window height, and a number of input samples. The maximum filter core frequency is greater than the sampling frequency. The maximum filter core frequency may be insufficient for a word serial instantiation of the rank order filter in the programmable logic. The size of a fully parallel instantiation of the rank order filter may be excessive in programmable logic. Thus, a partially parallel filter core is instantiated for the rank order filter with overclocking.
REFERENCES:
patent: 5408675 (1995-04-01), Florentino et al.
patent: 6687413 (2004-02-01), Yushiya
patent: 7072921 (2006-07-01), Kim
Gabor Szedo; “Tow-Dimensional Rank Order Filter”; Application Note: Virtex-5, Virtex-4, Virtex-II Pro, Virtex-II, Spartan-3A, Spartan-3E, Spartan; XAPP953 (v1.0); Aug. 24, 2006; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 1-17.
Roberto Roncella et al.; “70-MHz 2-um CMOS Bit-Level Systolic Array Median Filter”; IEEE Journal of Solid State Circuits; vol. 28; copyright 1993 IEEE; pp. 530-536.
Long-Wen Chang et al.; “Bit Level Systolic Arrays for Real Time Median Filters”; International Conference on Acoustics, Speech, and Signal Processing; Copyright 1990 IEEE; pp. 1791-1794.
Barun K. Kar et al.; “A New Algorithm for Order Statistic and Sorting”; IEEE Transactions on Signal processing, vol. 41, No. 8; Aug. 1993; Copyright 1993 IEEE; pp. 2688-2694.
Mustafa Karaman et al.; “Design and Implementation of a General-Purpose Median Filter Unit in CMOS VLSI”; Copyright 1990 IEEE; IEEE Journal of Solid-State Circuits; vol. 25, No. 2; Apr. 1990; pp. 505-513.
Chaitali Chakrabarti; “Sorting Network Based Architectures for Median Filters”; IEEE Transactions on Circuits and Systems-II: Analog:and Digital Signal Processing; vol. 40, No. 11; Nov. 1993; pp. 723-727.
Chaitali Chakrabarti et al.; “Novel Sorting Network-Based Architectures for Rank Order Filters”; Regular Issue Transactions Briefs; IEEE Transactions on Very Large Scale Integration (VLSI) Systems; vol. 2, No. 4; Dec. 1994; pp. 502-507.
Suhaib A. Fahmy et al.; “Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing”; Copyright 2005 IEEE; Field-Programmable Logic and Applications (FPL 2005); pp. 142-147.
Chaitali Chakrabarti; “High Sample Rate Array Architectures for Median Filters”; Copyright 1994 IEEE; IEEE Transactions on Signal Processing; vol. 42, No. 3; Mar. 1994; pp. 707-712.
Chung Wilson C.
Fehér Béla
Szántó Peter
Szedo Gabor
Cartier Lois D.
Ngo Chuong D
Webostad W. Eric
Xilinx , Inc.
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