Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
1998-06-10
2001-05-08
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S684000, C257S730000, C257S670000, C257S676000, C257S712000
Reexamination Certificate
active
06229200
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit package technology. In particular, the present invention relates to resin-encapsulated integrated circuit packages.
2. Discussion of the Related Art
Conventional lead frames are typically formed on a metal strip which provides up to ten (10) units. A conventional lead frame includes a “die pad” for accommodating a semiconductor die, and inner leads and outer leads. A lead frame can be incorporated in a variety of integrated circuit packages, such as a quad flat pack (QFP) package and its many variations. In a QFP package, each bond pad provided on the semiconductor die is wire-bonded to an inner lead which, in turn, is electrically coupled to an outer lead. The inner leads are typically provided mold-locking features to allow proper positioning of the lead frame during the molding step which provides a plastic or resin encapsulation of the package. After encapsulation, the outer leads are trimmed and bent using custom trim and form tools to complete the electrical terminals or “leads” used for mounting the package on to a printed circuit board. Precise forming of the leads is necessary to ensure satisfactory board yield. Malformed leads can result in open or shorted solder joints because of aplanarity or skewed leads. In addition, even without such malformed leads, board yield in QFP packages is also diminished by open solder joints resulting from solder wicking up the leads.
The size of a prior art QFP package is limited by the dimensions of the semiconductor die plus about 3 mm on each side. For example, a 7 mm×7 mm QFP package can accommodate up to a 4 mm×4 mm semiconductor die. Clearance requirements on a printed circuit board can add another 2 mm on each side to the final foot print. Thus, a 7 mm×7 mm QFP typically has a footprint of 9 mm×9 mm, thereby providing an effective board density of approximately 20%.
Conventional QFP type packages are encapsulated in resin both at the top and the bottom of the semiconductor die. Consequently, conventional QFP packages cannot be made thinner than 1.4 mm. In addition, external lead “stand-off” requirements add to the height of the final printed circuit board assembly.
One important quality measure for an integrated circuit package is reliability. In a QFP package, a significant failure mode is the delamination of the mold compound from the back of a die pad. Delamination introduces moisture into the package and causes moisture-related failures.
One performance measure in a conventional QFP or any plastic package is thermal performance. Such a package is limited in its thermal performance because of a lack of a thermally conductive path to dissipate heat from the semiconductor die to the exterior. In many applications, a heat sink is included in the package. However, including a heat sink increases the material cost of such a package. Further, even if a heat sink is included, there are still typically multiple layers of epoxy through which heat must flow from the semiconductor die to the exterior.
A conventional QFP package is typically manufactured in an assembly process which requires a custom mold, a custom trim tool and a custom form tool. Thus, the tooling cost for manufacturing a new QFP package is high. For a given integrated circuit, rather than providing a package that is optimized specifically for its size and its number of input/output (I/O) terminals, a designer typically selects a package by matching the size and I/O terminals requirements of his integrated circuit as closely as possible to one of a few available QFP packages for which the tooling investment is already made. Clearly, the resulting QFP package is optimized for neither density nor material cost.
What is desired is a low cost, high density, high reliability integrated circuit package with flexible configuration.
SUMMARY OF THE INVENTION
The present invention provides a plastic chip carrier and a method for making the same. A plastic chip carrier of the present invention includes: (a) a semiconductor die with bonding pads formed on its surface; (b) a die-attach pad on which the semiconductor die is attached; (c) leads disposed in close proximity of the die-attach pad; (d) wires bonded to the bonding pads and their corresponding leads to provide electrical connections; and (e) an encapsulation sealing the semiconductor die, the die attach-pad, the wires, and the leads from the environment in such a manner as to expose only the bottom surfaces of the die-attach pad and the leads.
The plastic chip carrier is formed using a process which includes the operations: (a) forming a matrix of lead frames out of a metal strip, with each lead frame having a die-attach pad and leads disposed in close proximity of the die-attach pad; (b) attaching a semiconductor die to each of the die-attach pad of the lead frame; (c) wire-bond the semiconductor die to the leads, so as to allow the leads to serve as electrical terminals to the semiconductor die; and (d) encapsulating the die-attach pad, the semiconductor die, the bond wires and the leads in a resin material to form a package, in such a manner that only the bottom surface of the die-attach pad and the bottom surfaces of the leads are exposed.
In one embodiment, the plastic chip carrier has an interlocking lip around the periphery of the die-attach pad, so as to allow the encapsulation material to securely engage the die-attach pad. In another embodiment, tie bars are provided attached to the die-attach pad. Each tie bar extends from the die-attach pad outwards to form a peripheral heat pad at the other end. Heat from the operating semiconductor die is conducted by the tie bar to the heat pad for dissipation out of the encapsulation. One of the heat pads has an appearance distinctive from the other heat pads of the chip carrier, thereby providing a convenient marker on the chip carrier which can be used to identify an orientation of the chip carrier or the location of a specified pin, such as pin
1
.
In one embodiment, the die-attach pad of the plastic chip carrier is pre-plated with palladium to avoid silver migration. In addition, the top surface of the encapsulation is provided a distinctive pattern, which can be conferred to the encapsulation from the molding cavity during the molding process. This pattern, which can be a dimple array, for example, can be used to orient the package after singulation. Alternatively, solder balls can be attached to the exposed portions of the leads to provide some clearance between the printed circuit board on which the package is mounted and the plastic chip carrier. In one embodiment, a soft solder attaches the semiconductor die to the die-attach pad to provide improved thermal performance.
According to another aspect of the present invention, a plastic carrier includes a double-row lead frame having leads arranged as an annular row of inner leads and an annular row of outer leads. The lead frame includes (a) a die-attach pad; (b) an annular row of inner leads; (c) an annular row of outer leads connected to the annular row of inner leads by a connecting portion. The connecting portion has a thickness which is half the thickness of a lead in the annular rows of inner and outer leads. In one implementation, the leads in the annular row of inner leads and the annular row of outer leads are arranged in an alternating fashion, to allow maximum density for wire bonds from the bonding pads of the semiconductor die at the die-attach pad to the inner and outer leads.
The double-row frame can be formed in a matrix of substantially identical lead frames. Further, the matrix of lead frames can be formed as one of multiple matrices of lead frames formed in a metal strip.
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pa
Fan Nelson
McLellan Neil
ASAT Limited
Kwok Edward C.
Skjerven Morrill & MacPherson LLP
Tran Minh Loan
LandOfFree
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