Saturating alignment shifter

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36474811, G06F 700, G06F 742

Patent

active

057936544

ABSTRACT:
A saturating alignment shifter for use in the multiply and accumulate unit in a floating point arithmetic unit of a microprocessor that mimics the ideal model of an infinitely wide shifter. A saturation alignment shifter is provided that, in the case of the operation of A*B.+-.C, saturates at a predetermined shifting increment and, in the case where the mantissa of C is saturated, places the mantissa C in the left most significant bits. After adding C to A*B in a summation unit, the mantissa of A*B ends up in the right most significant bits and a single intervening bit, termed the bubble bit, remains between the mantissa of C and the mantissa of A*B. The bubble bit acts to mimic any intervening bits that would have occurred in the case of an ideal infinitely wide shifter. The new shifter eliminates hardware required for special cases and treats all operations with a single alignment shifter giving a system that is faster and more simple than conventional systems.

REFERENCES:
patent: 5020013 (1991-05-01), Maher, III et al.
patent: 5099445 (1992-03-01), Studor et al.
patent: 5369607 (1994-11-01), Okamoto
patent: 5465222 (1995-11-01), Seckora
patent: 5559730 (1996-09-01), Marui et al.
patent: 5636351 (1997-06-01), Lee

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