Saturable carry-save adder

Details Saturable carry-save adder Saturable carry-save adder

1986-07-09

1989-04-04

Harkcom, Gary V.

Boots, shoes, and leggings

364745, G06F 750, G06F 738

Patent

active

048191981

ABSTRACT:
A carry-save adder for a bit-parallel addition of binary numbers in two's complement form incorporates a series of first adders for forming intermediate sum and carry words which are combined in an adder means to form a sum word. A decoder is provided for recognizing saturation of the carry-save adder and for generating overflow signals in dependence on the two most significant bits of the intermediate sum and carry words. When the overflow signals are generated, the recursive circuit branches are disconnected and saturation intermediate sum and carry words are substituted for the intermediate sum and carry words which yield sum words which do not exceed the permissible adder content.

REFERENCES:
patent: 3515344 (1970-06-01), Goldschmidt
patent: 3609568 (1971-09-01), Jackson
patent: 4104729 (1978-08-01), Gingell
patent: 4110832 (1978-08-01), Leininger et al.
patent: 4228520 (1980-10-01), Letteney
patent: 4229802 (1980-10-01), Eggermont
patent: 4379338 (1983-04-01), Wishitani et al.
patent: 4706209 (1987-11-01), Picco
patent: 4722066 (1988-01-01), Armer et al.
K. Hwang "Computer Arithmetic", (1979), pp. 98-103.
Proceedings of IEEE, vol. 63, No. 4, Apr. 1975, pp. 633-648.

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