Satisfiability (SAT) based bounded model checkers

Details Satisfiability (SAT) based bounded model checkers Satisfiability (SAT) based bounded model checkers

2005-11-22

2010-11-16

Rodriguez, Paul L (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S014000, C716S030000, C716S030000

Reexamination Certificate

active

07835898

ABSTRACT:
A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.

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