Satellite receiver

Details Satellite receiver Satellite receiver

1998-02-11

2001-08-28

Vo, Don N. (Department: 2664)

Pulse or digital communications

Receivers

Angle modulation

C375S329000, C375S344000, C329S307000

Reexamination Certificate

active

06282249

ABSTRACT:

The present invention relates to satellite receivers according to the preamble of claim 1.
Introduction: Variable Rate Digital Signals From Satellite
FIG. 1
shows a receiver concept for variable rate digital signals over satellite as implemented in the integrated circuit of the type TDA 8043 of Philips Semiconductors. An L-band input signal is received from a Low Noise Block converter outdoor unit, hereafter named as LNB, and fed into an input terminal of a tracking filter indicated by a reference numeral
1
. This L-band input signal represents a frequency multiplex of QPSK modulated carriers in a typical frequency range from 950-2150 MHz. Transponders may carry multiple QPSK modulated carriers in frequency multiplex, called single channel per carrier (SCPC) application, or a single high bit rate modulated carrier. As described in a more detailed manner in the publication “pr ETS 300 421” of August 1994 concerning “Digital broadcasting systems for television, sound and data services—framing stucture, channel coding and modulation for 11/12 GHz satellite services”, the high bit rate modulated carriers carry the MPEG2 transport stream of a number of time multiplexed channels. Also the simulcast combination of an analog FM modulated signal and an SCPC channel is possible.
FIG. 2
shows examples for possible receiver input signals. A wide range in symbol rates is desired to be received by the same receiver. A common used coding and modulation scheme is described in the Digital Video Broadcast standard, hereafter named as DVB and described in more detail in the above-mentioned publication “pr ETS 300 421”.
Description of a State of the Art Receiver Concept
Frequency Synthesizer Loop
The input signal is mixed down to a fixed Intermediate Frequency, hereinafter named as IF and having a typical value of 479.5 MHz, by means of a tunable Local Oscillator (LO), which is typically performed by a voltage controlled oscillator, hereinafter named as VCO, and placed at a frequency equal to the selected input carrier frequency plus the IF value. This LO is locked to a reference frequency in a Phase Locked Loop (PLL). Reference frequencies are usually generated in crystal type oscillators operated at a frequency between 4 and 20 MHz. A frequency divider ratio N of a programmable divider with the reference numeral
5
in
FIG. 1
is programmed for obtaining the desired VCO frequency. A divider ratio M of another frequency divider
8
in
FIG. 1
determines the frequency at the input ports of a phase detector
7
in
FIG. 1
, hereinafter named as comparison frequency. The divider ratio M of the frequency divider
8
and a divider ratio P of a prescaler
4
inserted before the programmable divider
5
can be either fixed or programmable. In all known receivers, the comparison frequency and loop parameter settings are chosen fixed, independent of the symbol rate of the selected modulated carrier. The described function (programmable comparison frequency) can be realised using e.g. an SP5659 frequency synthesizer provided by GEC Plessey semiconductors.
Receiver Filtering
FIG. 1
comprises an IF filter
11
which is a fixed bandwidth IF filter, usually of Surface Acoustic Wave (SAW) type. The bandwidth must be high enough to pass the signal spectrum when the highest specified symbol rate of the QPSK modulated carrier is to be received. When the variable rate decoder receives a lower symbol rate of an SCPC carrier in frequency division multiplex, hereinafter named as FDM, the same IF filter bandwidth is used. A more expensive solution uses a switchable IF filter with a low bandwidth filter used when receiving an L-band signal modulated with an information signal at a low symbol rate.
The non-desired adjacent channels are suppressed in filters with the reference numerals
23
and
24
in FIG.
1
. These are variable rate Nyquist filters, which can be programmed to match the incoming symbol rate. The channel filter selectivity function of the Nyquist filters
23
and
24
is allowed to be postponed to this late stage in the receiver, provided that all preceding stages have sufficient dynamic range to pass the signal which carries unwanted as well. This requirement also includes sufficient available bits in analog digital converters (ADC) with the reference numerals
20
and
21
in FIG.
1
.
Carrier Recovery
Demodulation of the QPSK signal requires the use of a synchronous carrier. This carrier is extracted from the input signal in a local phase locked loop. The phase and frequency detector functions needed for this local phase locked loop are implemented in the digital domain. Here signal samples are compared with look-up table values for generating the frequency and phase correction signal for the coherent carrier. The local phase locked loop can be realised fully in the digital domain using a discrete time oscillator, hereinafter named as DTO, and a complex multiplier. This is depicted in
FIG. 1
where reference numeral
27
denotes a complex multiplier, reference numeral
28
denotes a DTO and reference numeral
29
denotes a phase comparator, all working in the digital domain, that is with a stream of digital values building up the signal instead of an analog signal. The loop can also be closed over an analog VCO with the reference numeral
14
in
FIG. 1 and a
quadrature mixer consisting of two mixer stages with the reference numerals
12
and
13
. This last option is not depicted in FIG.
1
.
Under given phase noise and input white noise conditions, the curve of the phase jitter of the recovered carrier versus the natural carrier recovery PLL loop bandwidth will exhibit an optimum. For a chosen white noise and phase noise combination, the optimum loop bandwidth value shifts to lower values with lower rates. Not only the optimum shifts, but the resulting phase jitter in the loop will increase as well. Therefore lower phase noise values are required at low rates when the input signal to noise is kept the same.
Secondly, the loop stability has important implications. Since the digitally implemented phase detector will exhibit a delay proportional to the symbol time, the maximum allowable loop bandwidth has the lowest value for low symbol rate reception again.
Carrier Acquisition
For acquisition of a modulated carrier, a bus controlled algorithm is started. After receiving the frequency set point, a synthesizer sweep is started. Tuner steps are performed in a defined frequency window. The window is chosen such that the frequency error in the signal coming from the LNB can be detected. After a tuner step, the receiver status is checked for detection of signal presence. Usually receiver clock recovery lock is taken, since only a small fraction of the signal has to be received for already obtaining this lock.
The grid of the frequency sweep is determined by the acquisition range of the signal presence detector. Usually only a detector is available after the Nyquist filter. The bandwidth of the detector therefore scales with the received symbol rate, and the acquisition range will be approximately equal to plus and minus the symbol frequency divided by 6. This leads to the conclusion that a fine tuner step grid is necessary when low symbol rates are to be received.
When the input frequency deviates from the nominal value due to LNB ageing or temperature drift, the frequency difference must be compensated by a frequency shift in the VCO following the SAW filter. In case of high bit rate reception, the SAW filter must be wide enough to pass the signal without a single sided cut of the signal due to the displacement from the nominal center frequency value.
In U.S. Pat. No. 5,452,327 a programmable randomly tunable digital demodulator is provided with a carrier recovery loop and a PN code clock recovery loop each having a programmable digital loop filter coupled in series therein. Each digital loop filter is controlled by a timing control which is capable of controlling the carrier frequency tuning and the PN tuning frequency under the control of a microprocessor. A replica PN generator is programmed

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