Coded data generation or conversion – Sample and hold
Reexamination Certificate
2000-02-03
2001-10-30
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Sample and hold
C327S091000
Reexamination Certificate
active
06310565
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a sample and hold circuit, generally, and more particularly, to a sampling switch having an “on” impedance independent of the input signal to be sampled.
BACKGROUND OF THE INVENTION
A commercial drive exists for reducing power consumption in electronic devices. In support of this effort, industry has attempted to exploit digital signal processing techniques to minimize the usage of high power consuming analog componentry. Digital processing necessitates the conversion of continuous analog signals into a digital data format using an analog-to-digital converter (“ADC”).
ADCs convert analog signals into discrete digital data by performing a series of functional steps. These process steps include sampling, holding, quantizing and encoding. Though unique, these four steps need not be performed as independent operations. It is known, for example, to perform the sample and hold functions simultaneously using a single circuit.
Referring to FIGS.
1
(
a
) and
1
(
b
), a known circuit
10
for sampling and holding an analog signal, V
IN
, is shown. Sample and hold circuit
10
comprises a metal oxide semiconductor (“MOS”) type transistor M
a
having a source for receiving the continuous analog signal, V
IN
. Further, the gate of transistor M
a
receives a sample signal, &PHgr;
a
, which comprises a series of pulses. Each pulse of sample signal, &PHgr;
a
, has a width, &tgr;, and a sampling periodicity T
s
. As illustrated in FIG.
1
(
b
), at the intervals when a sampling pulse of sample signal, &PHgr;
a
, is received by the gate of transistor M
a
, a segmented portion corresponding with the pulse width, &tgr;, of the pulse and the relative height of the continuous analog signal, V
IN
, is captured as a sample. Thereafter, the sample is transferred to a capacitor, C
a
, for interim storage. The held samples are represented by V
OUT
.
One problem with ADCs, particularly when realized in MOS technology, is the linearity of the impedance of the sampling switches. As in the circuit of FIG.
1
(
a
) hereinabove, the MOS transistor M
a
is turned on and off by the sample signal, &PHgr;
a
, to produce the samples found in V
OUT
. However, a relationship exists between the inherent impedance of the switch of circuit
10
and the input signal, V
IN
. Upon receiving a sampling pulse of sample signal, &PHgr;
a
, the impedance of the switch of circuit
10
is a function of the difference between the gate to source voltage (“V
GS
”) of transistor M
a
and the threshold voltage (“V
TH
”) of transistor M
a
for the duration of pulse width, &tgr;. The impedance of the switch of circuit
10
, while a sampling pulse is received by transistor M
a
, is also referred to as R
ON
, and may be mathematically represented by the following formula:
R
ON
=
1
μ
n
C
OX
W
L
(
V
GS
-
V
TH
)
where &mgr;
n
is the electron mobility, C
ox
is the capacitance of the gate oxide, W is the width and L is the length of the channel of transistor M
a
, assuming the drain to source voltage (“V
DS
”) of transistor M
a
to be inconsequential and the applicability of square law behavior. As may be viewed by the above mathematical expression in view of circuit
10
of FIG.
1
(
a
), V
GS
is equal to the difference between the “on” peak voltage of the pulse of sample signal &PHgr;
1
, or V
DD
, and the input signal V
IN
.
Moreover, V
TH
also functionally corresponds with V
IN
by means of source bulk voltage (“V
SB
”). V
TH
may be mathematically represented by the following formula:
TH
=V
THo
+&ggr;*[{square root over (2|&PHgr;
f
|+V
SB
+L )}−{square root over (2|&PHgr;
f
+L |)}]
where V
THo
is an initial threshold voltage constant, &ggr; is a body effect parameter and &PHgr;
f
is a quasi-Fermi potential of transistor M
a
.
Given the hereinabove mathematical expressions, the “on” resistance, R
ON
, is therefore a non-linear function of input signal V
IN
. Signal distortion is a natural byproduct of the mathematical relationship of R
ON
with input signal V
IN
, generally, and more particularly if the voltage levels of V
IN
change rapidly. Thus, efforts to lower signal distortion have focused on reducing the value of R
ON
, as well as its dependence on the input signal V
IN
.
Several solutions have been proposed to reduce the dependence of R
ON
on input signal V
IN
. Each of these approaches, however, have particular shortcomings. These limitations include raising additional non-linearities, as well as failing to eliminate the dependent relationship between V
TH
on input signal V
IN
and thus R
ON
with input signal V
IN
, irrespective of whether the frequency of the sample signal is or is not much greater than V
IN
.
As such, there is a need to provide a sampling device having a switch with a gate source voltage, and, thus, an “on” impedance, R
ON
, that is independent of the input signal being sampled. Likewise, there also exists a demand for a sampling device having a switch with a threshold voltage, and, hence, an “on” impedance, R
ON
, independent of the input signal being sampled. Moreover, there is a need for a sampling device with a switch having an “on” impedance, R
ON
, independent of the input signal being sampled which does not raise additional non-linearities, irrespective of whether the frequency of the sample signal is or is not much greater than that of the input signal.
SUMMARY OF THE INVENTION
A sampling device provides for sampling an input signal in response to a sample signal is disclosed. The sampling device comprises a sampling transistor for creating samples of the input signal in response to the sample signal. The sampling transistor has a gate to source voltage, a threshold voltage, and an “on” impedance corresponding with the difference between the gate to source voltage and the threshold voltage. Moreover, the sampling device comprises a control device for controlling the sampling transistor by generating a control signal in response to the sample signal. The control device comprises a bootstrap reference voltage source for providing a reference voltage in response to the sample signal, as well as a control circuit for generating a control circuit voltage in response to the sample signal. The control circuit voltage comprises the sum of the input signal and the threshold voltage, while the control signal comprises the sum of control circuit voltage and the reference voltage. By this arrangement, the gate to source voltage of the sampling transistor comprises the difference between the control signal and the input signal.
In a further embodiment of the present invention, the control circuit provides an operational amplifier for generating a node output in response to receiving the input signal and a feedback loop as inputs. The control circuit also comprises a control MOS transistor. The control MOS transistor has a gate coupled with the node output, a drain coupled with a supply voltage, such as the reference voltage for example, and a source coupled with the feedback loop.
In yet another embodiment of the present invention, the control circuit provides a fixed current source. The fixed current source is coupled with the source of the control MOS transistor and the feedback loop. By this arrangement, the feedback loop comprises the input signal.
In still another embodiment of the present invention, a sampling device is provided for sampling an input signal. The sampling device comprises a sampling switch for creating samples of the input signal. The sampling switch has a turn “on” voltage and an impedance. Further, the sampling device comprises a control device for generating a control signal to control the sampling switch. The control device comprises a reference voltage source for generating a reference voltage, and a control switch for generating a control switch voltage. The control switch voltage comprises the sum of the input signal and the turn on voltage. Moreover, the control signal comprises the sum of the control switch voltage and the reference voltage
Ong Adrian K.
Prodanov Vladimir I.
Tarsia Maurice J.
Jean-Pierre Peguy
Lucent Technologies - Inc.
Teitelbaum Ozer M. N.
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