Sampling rate conversion using digital differential analyzers

Details Sampling rate conversion using digital differential analyzers Sampling rate conversion using digital differential analyzers

1998-10-01

2002-03-12

Eisenzopf, Reinhard J. (Department: 2614)

Television

Image signal processing circuitry specific to television

Special effects

C348S704000, C348S440100, C348S561000, C348S441000, C382S298000

Reexamination Certificate

active

06356315

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to a system for sampling rate conversion and particularly to a system that resamples by way of interpolation, filtering, and decimation.
During display of a video image sequence, it is often desirable to magnify or reduce an original video frame size or viewing area size on screen. For example, in multimedia systems it is desirable to allow users to change the size of multiple video images from time to time. Magnification and reduction capabilities also find application in picture-in-picture features in consumer televisions.
Often, original video images to be reduced or enlarged are available in digital form, having been received from television or direct satellite broadcast, decoded from MPEG (Moving Picture Expert Group) and JPEG (Joint Photographic Expert Group) standards coded bitstream, or downloaded from CD ROMs. One way to achieve magnification or reduction of digitized video images is to use the techniques of interpolation, linear filtering and decimation of image.
A video system capable of displaying digital video images typically displays a fixed number of pixels per scan line and a fixed number of scan lines per image. The spacing between pixels on a scan line is also fixed. To magnify (or reduce) an image for display is equivalent to increasing (or decreasing) the number of pixels or samples that represent the image so that an increased (or decreased) display area is obtained on the video monitor. Thus magnification or reduction can be implemented as a sampling rate conversion process applied to each video scan line. A general mathematical scheme of sampling rate conversion is disclosed in Ronald E. Crochiere and Lawrence R. Rabiner, “Multirate Digital Signal Processing,” Prentice-Hall, 1983, the contents of which are herein expressly incorporated by reference for all purposes.
To realize such a sampling rate conversion scheme, the necessary interpolation and decimation factors must first be determined. For an input signal x(n) with sampling period T
in
(or sampling frequency F
in
) and a resampled output signal y(n) with sampling period T
out
(or sampling frequency F
out
), the following ratio is formulated,
T
i
⁢
n
T
out
=
F
out
F
in
=
L
M
where L and M are integers and are referred to as the interpolation factor and decimation factor, respectively. For L>M, the output signal y(n) achieves an increased sampling rate and hence an increased number of samples or pixels per scan line. The visible effect is a magnified video image when displayed because more pixels occupy more physical space on screen. For L<M, the opposite effect is obtained.
To implement magnification/reduction in this way, three functional blocks are typically used: an interpolator, a low-pass filter, and finally a decimator. The interpolator first places L−1 zero-valued samples between successive samples in x(n). This operation increases the sampling rate of the signal x(n) by a factor of L and creates L−1 folds of spectral images in the frequency domain of the interpolated signal. The low-pass filter is then employed to filter out these spectral images while retaining the component at the baseband. Finally, the filtered signal is decimated with a factor of M, that is, the decimator outputs every M-th sample to form the output signal y(m). Mathematically, the sampling rate conversion process is expressed as
y
⁡
(
m
)
=
∑
n
=
-
∞
∞
⁢
h
⁡
(
Mm
-
nL
)
×
(
n
)
(
2
)
where {h(n)} represents the low-pass filter.
However, a magnification/reduction system that incorporates a distinct interpolator, low-pass filter, and decimator is complex and costly to implement, requiring extensive VLSI surface area. A P-tap FIR implementation of the low-pass filter, necessarily operates at L times the input sample rate and thus requires L*P operations per input sample. What is needed is a more efficient magnification/reduction scheme suitable for VLSI implementation.
SUMMARY OF THE INVENTION
In accordance with the invention, magnification/ reduction is achieved by a single FIR filter under the control of a Digital Differential Analyzer (DDA) as would be used to simulate a perfectly straight slope line on a two-dimensional raster. The single FIR filter combines the processes of interpolation, filtering, and decimation. The DDA is programmed with the desired magnification/reduction ratio and provides signals that control shifting of input samples into the FIR filter and selection of FIR coefficients for the FIR filter. In one embodiment, a prefilter and decimator are provided for optionally preprocessing the input so that an overall reduction in computation is provided by magnification within the FIR filter itself.
In one embodiment suitable for use with color digital video systems, a first FIR filter controlled by a first DDA applies magnification/reduction to a luminance signal, Y, and a second FIR controlled by a second DDA applies magnification/reduction to an interleaved combination of two chrominance signals, C
b
and C
r
. The two chrominance signals are processed separately within the second FIR.
In accordance with one aspect of the invention, a DDA adapted for use in magnification/reduction includes a ratio register, an adder, and a status register. A magnification reduction ratio M/L is stored in the ratio register with L being restricted to being a power of two. This ratio is summed by the adder into the status register after every calculation of an output sample by the FIR filter. The status register thus tracks the output sample position as compared to the input sample position. The necessary width of these registers depends on the expected cumulative error across a single scan line, since the DDA is typically reset upon completion of a particular scan line.
In one particular embodiment, the status register has twelve bits [
11
] through [
0
] with [
11
] being the most significant bit and [
0
] being the least significant bit with a decimal point implied between bits [
10
] and [
9
]. For an interpolation factor, L=4, bits [
9
-
8
] are used to select from among four sets of FIR coefficients for the FIR filter for each calculation of an output sample. For other values of L which are powers of two, log
2
L bits beginning with bit [
9
] would be used for this purpose. For magnification, a toggling of bit [
10
] is the signal to shift a new sample or pixel into the FIR. For reduction, bits [
11
-
10
] indicate how many samples or pixels are to be shifted into the FIR after the calculation of each output sample. This control of the input shifting achieves the necessary interpolation by L. Decimation by M is achieved since the output sample position is incremented by the magnification/reduction ratio.
The invention will be better understood by reference to the following detailed description in connection with the accompanying drawings.


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K. Blair Benson, “Television Engineering Handbook,”McGraw-Hill Book Company, pp. 4.66-4.68 and 5.29-5.33 (1985).
J. Foley et al., “Computer Graphics, Principles and Practice, Basic Raster Graphics Algorithms for Drawing 2D Primitives,”Second Edition-Addison-Wesley Publishing Co., pp. 72-74.

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