Sampling network analyzer with sampling synchronization by means

Details Sampling network analyzer with sampling synchronization by means Sampling network analyzer with sampling synchronization by means

1981-04-30

1983-11-08

Ruggiero, Joseph F.

Boots, shoes, and leggings

307269, 307498, 307353, 328133, 329122, 364481, 364608, G06J 100

Patent

active

044146396

ABSTRACT:
An improved Sampling Network Analyzer is disclosed, in which synchronization of the sampling of one or more input signals, either voltages or currents, is effected by means of a phase-locked loop (PLL). A reference signal serves to synchronize a phase-locked loop, which in turn synchronizes sample-and-hold circuits utilized for measurement. A C preset counter permits the operator to set a desired number of samples per measurement. A Y preset counter maintains the voltage-controlled oscillator within a predetermined (relatively narrow) range of frequencies. Operation of the sample-and-hold circuits is at a frequency that is related to the reference frequency by the ratio of two integers. A D preset counter is provided in the reference signal path to allow the Sampling Network Analyzer to be synchronized to a subharmonic of the reference frequency where the reference frequency is too high to permit the desired number of samples per measurement within a single period.

REFERENCES:
patent: 3344350 (1967-09-01), Stoft
patent: 3713029 (1973-01-01), Uchida
patent: 3769602 (1973-10-01), Griswold
patent: 3789199 (1974-01-01), Kotwicki
patent: 3944940 (1976-03-01), Desai
patent: 3982193 (1976-09-01), Maringer
patent: 4149256 (1979-04-01), Sumi et al.
patent: 4318183 (1982-03-01), Byington et al.

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