Sampling frequency converting device and memory address control

Details Sampling frequency converting device and memory address control Sampling frequency converting device and memory address control

1995-01-23

1997-04-01

Hoff, Marc S.

Coded data generation or conversion

Digital code to digital code converters

Data rate conversion

341123, H03M 700

Patent

active

056170882

ABSTRACT:
A sampling frequency converting device. A memory unit stores an input signal D.sub.si having an input sampling frequency F.sub.si. An interpolation unit interpolates the readout signal from the storage unit. A sampling frequency ratio detection unit detects the current sampling frequency ratio R.sub.n between the input sampling frequency F.sub.si and the output sampling frequency F.sub.so and detects a new sampling frequency ratio R.sub.n NEW. based on the current sampling frequency ratio R.sub.n and a past detected value R.sub.n-1 preceding the current detected value by one detection period. A control unit having the sampling frequency detection unit controls the storage unit and the interpolating unit from the new sampling frequency ratio R.sub.n NEW. Since the present sampling frequency converting device is not susceptible to accumulation of re-sampling time address errors even if the sampling frequency ratio continues to be changed for a pre-set time duration, the capacity of the storage unit is not increased, while there is no necessity of restricting the speed or amount of change in the sampling frequency ratio.

REFERENCES:
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patent: 5481267 (1996-01-01), Miyabe et al.
Patent Abstracts of Japan, No. JP 5259812, (Kakubo et al.).

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