Television – Format conversion
Reexamination Certificate
2001-03-29
2004-04-20
Lee, Michael H. (Department: 2614)
Television
Format conversion
C348S450000, C348S571000, C348S572000, C348S663000, C704S503000
Reexamination Certificate
active
06724430
ABSTRACT:
FIELD OF THE INVENTION
The present invention relate to a video signal processor for separating a television signal into Y (Luminance) and C (Color) signals and outputting the Y and C signals as digital video signals and, more particularly, to rate conversion of the digital video signals and generation of a clock which is used for the rate conversion.
BACKGROUND OF THE INVENTION
Hereinafter, a prior art video signal processor for separating an analog television signal into Y (Luminance) and C (Color) signals, and converting the signals into digital video signals to be output is described with reference to drawings.
FIG. 9
is a block diagram illustrating the prior art video signal processor.
FIG. 10
are waveform charts of a video signal, FIG.
10
(
a
) showing a video signal, FIG.
10
(
b
) showing a synchronous signal, and FIG.
10
(
c
) showing a burst signal.
FIG. 11
are diagrams for explaining the Y/C separation, FIG.
11
(
a
) showing a video signal, FIG.
11
(
b
) showing a Y (luminance) signal, and FIG.
11
(
c
) showing a C (color) signal.
As shown in
FIG. 9
, the prior art video signal processor comprises an analog television signal input terminal
101
, a first digital video signal output terminal
102
, a first A/D converter circuit
103
, a synchronization separator/burst detector circuit
104
, a burst locked clock generator circuit
105
, a Y/C separator circuit
106
, a color decoder circuit
107
, a TBC circuit
108
, a divider circuit
112
, a vertical/horizontal signal generator circuit
113
, a multiplexer circuit
114
, a D/A converter circuit
115
, a second A/D converter circuit
116
, a synchronization separator circuit
117
, a horizontal synchronous clock generator circuit
118
, a second digital video signal output terminal
201
, a DVC preprocessing circuit
202
, and a frame synchronization clock generator circuit
205
.
Hereinafter, the operation of the so-constructed video signal processor is described.
The analog television signal input terminal
101
is an input terminal to which an analog television signal S
101
is input. As the analog television signals, there are standard television signals which are determined by the standards like broadcasting, television signals whose synchronous signals have deviated frequencies or which include jitter, such as television signals which are reproduced for example by a video tape recorder, and non-standard television signals which are not standard television signals.
The first digital video signal output terminal
102
outputs a first digital video signal S
102
which is obtained by multiplexing a Y (luminance) signal, a Cr (color difference-red) signal, Cb (color difference-blue) signal and a synchronous signal, to an apparatus or an equipment which is connected to this video signal processor, at a 27-MHz bit rate which is a transmission format of ITU-R recommendation BT.
656
according to the digital interface standards.
The first A/D converter circuit
103
samples the analog television signal S
101
on a 14.3-MHz burst locked clock S
105
(which is described later), to be converted into a digital television signal S
103
. The first A/D converter circuit
103
also can sample the analog television signal S
101
for example on a 28.6-MHz burst locked clock.
The synchronization separator/burst detector circuit
104
separates a synchronous signal S
104
a
as shown in FIG.
10
(
b
) from the digital television signal S
103
as shown in FIG.
10
(
a
) by a threshold. Further, the circuit
104
extracts a 3.58-MHz burst signal S
104
b
as shown in FIG.
10
(
c
), which is multiplexed as a reference signal for color reproduction, from the separated synchronous signal.
The burst locked clock generator circuit
105
multiplies the 3.58-MHz burst signal S
104
b
by four to generate a 14.3-MHz burst locked clock S
105
.
The Y/C separator circuit
106
converts the digital television signal S
103
in which a Y (luminance) signal and a C (color) signal are frequency-multiplexed as shown in FIG.
11
(
a
), into a Y signal S
106
a
as shown in FIG.
11
(
b
) and a C signal S
106
b
as shown in FIG.
11
(
c
). When the input analog television signal is a standard television signal, still-picture parts are subjected to a three-dimensional processing using a frame memory, and moving-picture parts are subjected to a two-dimensional processing using a line filter, with utilizing the fact that the color phase is inverted frame/line by frame/line.
The color decoder circuit
107
demodulates the digital C signal S
106
into a digital Cr signal S
107
a
and a digital Cb signal S
107
b
, because the phases of the Cr signal and the Cb signal are shifted by 90 degrees from each other.
The TBC (Time Base Corrector) circuit
108
detects the time of the horizontal synchronous signal of the synchronous signal S
104
a
, and converts the Y signal S
106
a
, the Cr signal S
107
a
and the Cb signal S
107
b
according to the length of the horizontal synchronous signal of the synchronous signal S
104
a
, to be output as a Y signal S
108
a
, a Cr signal S
108
b
, and a Cb signal S
108
c.
The D/A converter circuit
115
converts the Y signal S
108
a
, the Cr signal S
108
b
and the Cb signal S
108
c
which are the digital signals output from the TBC circuit
108
, into analog signals, i.e., a Y signal S
115
a
, a Cr signal S
115
b,
and a Cb signal S
115
c.
The second A/D converter circuit
116
samples the Y signal S
115
a
, the Cr signal S
115
b
and the Cb signal S
115
c
on a 13.5-MHz clock S
112
(which is described later), to be converted into digital signals, i.e., a Y signal S
116
a
, a Cr signal S
116
b
and a Cb signal S
116
c
. Here, it is also possible that the Cr signal and the Cb signal are multiplexed before being input to the second D/A converter circuit
115
, and the D/A converter circuit
115
and the second D/A converter circuit
116
perform the conversion of the Y signal and the C signal. Further, the second A/D converter circuit also can perform the sampling for example on a 27-MHz clock.
The synchronization separator circuit
117
separates a horizontal synchronous signal S
117
a
and a vertical synchronous signal S
117
b
from the Y signal S
116
a
, and outputs the signals.
The horizontal synchronous clock generator circuit
118
outputs a 27-MHz horizontal synchronous clock S
118
which is synchronized with the horizontal synchronous signal S
117
a
, to the divider circuit
112
and the multiplexer circuit
114
. The horizontal synchronous clock generator circuit
118
is commonly constituted by an analog PLL circuit.
The divider circuit
112
divides the frequency of the 27-MHz horizontal synchronous clock S
118
into 13.5 MHz. This 13.5-MHz clock S
112
is the above-mentioned sampling clock which is input into the second A/D converter circuit
116
.
The vertical/horizontal signal generator circuit
113
generates a synchronous signal S
113
corresponding to a BT.
656
transmission format, from the horizontal synchronous signal S
117
a
and the vertical synchronous signal S
117
b
, and output the signal S
113
.
The multiplexer circuit
114
multiplexes the Y signal S
116
a
, the Cr signal S
116
b
, the Cb signal S
116
c
and the synchronous signal S
113
on the 27-MHz horizontal synchronous clock S
118
, and outputs a multiplexed signal as the first digital video signal S
102
. The first digital video signal S
102
is output from the first digital video signal output terminal
102
to an apparatus or an equipment which is connected to this video signal processor.
The second digital video signal output terminal
201
is an output terminal for outputting a second digital video signal S
201
in which the Y signal, the Cr signal and the Cb signal are multiplexed, at 18 MHz. The second digital video signal S
201
is input to a DCT (Discrete Cosine Transform) block for performing intra-frame compression/decompression, processed at 18 MHz, and thereafter recorded/reproduced by a block for performing recording/reproduction into/from a tape.
The DVC preprocessing circuit
202
multiplexes the 13.5-MHz Y signal S
116
Miyoshi Toshihiro
Murata Hisaji
Yumine Manabu
Lee Michael H.
Matsushita Electric - Industrial Co., Ltd.
Natnael Paulos
Wenderoth , Lind & Ponack, L.L.P.
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